Artesyn ATCA-7360, Инструкция по установке и эксплуатации

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Maps and Registers
ATCA-7360 Installation and Use (6806800J07S)
171
3 Parity enable/disable
When bit 3 is set, a parity bit is generated in
transmitted data between
the last data WORD bit and the first stop bit. In
received data, if bit 3 is
set, parity is checked. When bit 3 is cleared, no
parity is generated or checked.:
1: Parity enabled
0: Parity disabled 0 LPC: r/w
4 Parity even/odd
When parity is enabled and bit 4 is set, even parity
(an even number of logic ones in the data and
parity bits) is selected. When parity is disabled
and bit 4 is cleared, odd parity (an odd number of
logic ones) is selected.:
1: Even parity
0: Odd parity 0 LPC: r/w
5 Stick parity
When bits 3, 4, and 5 are set, the parity bit is
transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is
cleared, the parity bit is transmitted and checked
as set. If bit 5 is cleared, stick parity is disabled.:
1: Stick parity enabled
0: Stick parity disabled 0 LPC: r/w
6 Break control bit
Bit 6 is set to force a break condition, i.e. a
condition where TXD is forced to the spacing
(cleared) state. When bit 6 is cleared, the break
condition is disabled and has no affect on the
transmitter logic. It only effects TXD:
1: Break condition enabled
0: Break condition disabled 0 LPC: r/w
Table 6-33 Line Control Register (LCR) (continued)
LPC IO Address: Base + 3
Bit Description Default Access