Artesyn Embedded Technology 6806800V01A, Сборка, установка и использование

Страница: 45 / 108

Functional Description
SharpStreamer™ Pro PCIE-7210/7211 Installation and Use (6806800V01A)
45
Figure 3-3 shows the location of the temperature sensors on the card.
3.9 Clock Distribution
Clocking for each CPU complex consists of two input crystals. One 24 Mhz crystal to drive all
the main buses and a 32.768 Khz crystal to drive the real time clock. Processor clocks are driven
from PCH device. Each CPU has a dual channel memory, each memory channel provides an
1066.67 Mhz clock to their respective memory channel.
3.10 Reset Management
Each PCH reset is controlled by the CPLD. CPU and Peripheral reset are controlled by PCH.
During power up the CPLD state machine drives the reset control to each CPU during an
induced reset from the front panel reset switch.
For more information about Reset button, refer the section Controls on page 66 .
Figure 3-3 Location of Temperature Sensors - Secondary Side
U68 Temperature Sensor
U91 Temperature Sensor