Motherboard Manual
5
Code
Beep
POST Routine Description
16h
1-2-2-3
BIOS ROM checksum
20h
1-3-1-1
Test DRAM refresh
22h
1-3-1-3
Test 8742 Keyboard Controller
2Ch
1-3-4-1
RAM failure on address line xxxx
2Eh
1-3-4-3
RAM failure on data bits xxxx of low byte of memory
bus
30h
1-4-1-1
RAM failure on data bits xxxx of high byte of memory
bus
46h
2-1-2-3
Check ROM copyright notice
58h
2-2-3-1
Test for unexpected interrupts
98h
1-2
Search for Option ROMs.
One long, Two short beeps on Checksum failure.
B4h
1
One short beep before BOOT
For Boot Block in Flash ROM
Copyright © 1997 by Phoenix Technologies Ltd., All Rights Reserved
Phoenix Technologies Ltd. (Desktop Division)
135 Technology Drive, Irvine, CA 92618
http://www.phoenix.com
NOTE
The documented routines are sorted by their test point numbers assigned in the BIOS code.
Their actual order of execution during the POST can be quite different.
POST Errors and Beep Codes continued...
If the BIOS detects an error in test codes 2Ch, 2Eh, or 30h (base 512K RAM error), it displays
an additional word-bitmap (xxxx) indicating the address line or bits that failed.
For Example:
“2C 0002” means address line 1 (bit one set) has failed.
“2E 1020” means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16 bits.
The BIOS also sends the bitmap to the port 80h LED display. It first displays the check point
code, followed by a delay, the high-order byte, another delay, and then the low-order byte of
the error and a delay. The system will continually repeat this sequence.
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