Arcam DiVA DV78, Руководство по обслуживанию

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Clocks and SPDIF stage.
IC300 is a PLL1700E clock generator IC the chip is
powered from the +5V(D) rail. The Chip runs in
software mode and is slaved from the Vaddis V (data
coming in on the MD line).
X300 is a 27Mhz crystal that IC300 uses to generate
all the video and audio clocks required by the system
the crystal sits on the XTI and XTO pins of the chip,
the 27Mhz output at Pin 10 (MCKO) is used to drive
the Vaddis chip directly bypassing the internal PLL.
The frequency of the audio master is dependent on
the on the current audio sample rate (I.e the sample
rate required by the format CD=44.1Khz and
DVD=48khz etc) and this is set by the system micro
via the MD, MC and ML_1700 lines from the Vaddis V.
Clock Buffer
IC301 us used to buffer the audio master clock. The
circuit is arranged so that each device that requires
the audio master clock has it’s own driver these are
seen as.
o
MCLK_DAC0 - Pin 18
o
MCLK_DAC1 – Pin 16
o
MCLK_DAC2 – Pin 14
o
MCLK_VADDIS – Pin 3
o
MCLK_HDMI – Pin 9
We also run the Mute Line from the Vaddis V IC301
this can be seen on Pin 12 and drives transistor
TR401 , the transistor pulls the relays RLY400,
RLY500, RLY600 to ground and un-mutes the audio
outputs.
IS2 Audio Data
IC302 and IC309 are buffers for the 12S signals these
ensure that the signals travelling to the DAC’s are
point to point. IC302 deals with the ALRCK and
ABCLK and I C309(NF DV78) the
ADAT0,1,2
all signal are split into three separate lines
for the three stereo DACS.
PSU Clock Divider
IC304 a/b form a clock divide by 1, 2 or 4 to ensure
the PSU clock is always either 44.1kHz or 48Khz ( See
fig 1 within the power supply description section).
The circuit is fed from the ALRCLK (Audio clock) the
selected PSUCLK is controlled by PSUFSO and
PSUFS1 .
The output of the PSU circuit can be seen to leave
IC305 on pin 5 via R311. Please see Fig 1 for PSU
control information.
The circuit will also switch the PSUCLK off when switching
between sample rates (the PSU will free run when the
PSUCLK is not present).
SPDIF Output
The SPDIF output consists of IC901 implemented as a
inline buffer and parallel output buffer. Gate A buffers the
signal so that the SPDIF line from the VADDIS sees fewer
loads and form a feed to the Optical output transmitter,
gates B,C and D drive the SPDIF in parallel so that we can
drive a 75ohm load adequately. The resistors at the output
of IC901 are arrange so that the output will be 500mV pk-
pk when the output is terminated with a 75 ohm load at the
same time the output impedance of the circuit is 75ohms
as required by the Sony Philips Digital Interface
specification.
Left and Right channel D to A stages
The Wolfson WM8740 stereo DAC ay location IC403
re5V( A ) and a +3V3 supply along with the Digital
Audio data lines already described in this guide.
The Left channel output only will be described in this
section.
IC400B and associated components form a 2
nd
order
Bessel filter with a differential input and a gain of 1 this
follow by a output buffer IC401B , the gain of IC401B is
control by the switching chip at location IC402 , in normal
use the Gain of IC401B is set to 1.1 but in HDCD mode
the IC402 switches a second 10k resistor in parele with
R413 and the gain is set to 2.2 allowing for the higher
audio output required by the HDCD standard.
C436 is an A.C coupling capacitor used to remove the few
mV of offset that the DAC produces; D400 provides
protection against from ESD.
The all output relays are under control of the Vaddis V
chip but will also mute the outputs instantly under mains
failure conditions. Switching drive is provided by TR401
(MUTE_BUF) and TR400 (AC_PRES) the relays are in
mute mode if either the input to TR401 is Low or if the
input to TR400 is high.
Please note: The Scart left/right audio is fed from the
outputs of the left/right audio stages.