Arcam DiVA DV78, Руководство по обслуживанию

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Display Board interface
The display board interface is on the 16 way FFC flexi
foil connector at location CON202. Power for the
display also travels on the connector. There are 4 –
wires to interface with the VFD driver chip these are
seen as.
o
XFPDIN - Data to the display board
o
FPDOUT - Data from the display board
o
XFPCLK - Clock
o
XFPSEL - Chip select
The above control lines are level shifted to 5v logic
from 3.3v levels by IC200 (74HCT125) these are the
levels required by the VFD drive chip.
The IR output from the Display board arrives as
IRRCV this is an open collector signal, which can be
wire-Ord with the re-panel remote input.
Digital Audio
The Digital audio leaves the chip as 1 data line
labelled as.
o
ADAT0 - Left and Right channel data
Along with the ADAT line we will also see the ABCLK
and ALRCK as required for IS2 data conversion.
The Vaddis V also supplies a direct SPDIF output for
interfacing with ancillary processing equipment.
Flash/ SDRAM
IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at
135MHz
IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for
program storage (Player software).
The flash interfaces to the Vaddis V using the SDRAM
bus it may appear that the bus connects to the flash in
a random manner, however this is simply because the
Vaddis bus is multiplexed that way. The Flash will be
accessed at power up and the contents are copied to
the SDRAM the program will then be run from the
SDRAM.
Series resistors are employed to isolate the flash bus
from the main SDRAM bus.
EEPROM
IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used
for storage of non-volatile storage of player settings,
region settings and bookmark data.
Clocks
CLK27MV is the 27Mhz clock for video. It is used to
generate the 135Mhz clock for the Vaddis microprocessor
and DSP. The MCLKV is the audio master clock for the
Vaddis.
We run the Vaddis in PLL bypass mode and generate or
own master clock (see main clock section of manual) for
higher accuracy and improved performance across Audio
and Video.
RESET
IC201 is a reset generator chip that monitors the +3.3V rail
and ensures a reset signal PWR_ON_RESET* is
generated on power up, or if the mains power dips below
an operational level.
This signal is used to reset the Vaddis V and Flash micro
only. The Vaddis V line labelled as RESET* resets the
remaining circuitry of the player apart from the HDMI chip,
this has it’s own reset line labelled as HDMI_RESET this is
necessary if we require to reset the HDMI chip only (for
example when the HDMI sink is connected and then
disconnected).
Serial Port
The VADDIS V can interface with the external world via
the RS232 connector at location CON900 and the RS232
Transceiver at location IC900, the serial data lines are
shown as SERIAL RX and SERIAL TX these lines allow
for direct control over the unit via RS232.
Fig 2. GPIO control signals from the Vaddis V
Single Name I/P-O/P Function
PSUFSO-1 Output Control PSU Clock
divider
ENABLE_AV Output SCART control High
in normal operation
and low in standby
16/9 Output
Scart 16/9
anamorphic control
line
GAIN_SCALING Output High for HDCD gain
scaling
ML_8740_0-2 Output SPI load signal for
Audio DACs 0
MC Output
SPI clock signal for
DAC control
MD Output SPI data signal for
DAC control
FSELE0-1 Output Frequency select
generator
MUTE* Output
Active low audio
mute signal
RESET* Output System reset