6 General Purpose Input/Output (GPIO)
61
CW6632B Bluetooth 3.0 Audio Player SOC
Version 1.0.0
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Default
0
0
0
0
x
x
x
X
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LDOBGOE
: LDO Bandgap output enable
0 = Disable
1 = Enable
SPI0PS1
: SPI0 port select 1.See chapter 16 SPI0
COSEL
: CLKO sources selection
00 = P3[3]
01 = PLL 12MHz
10 = System clock
11 = XOSCO
WKEDGx
: Port interrupt Edge Select
0 = Select rising edge as interrupt trigger event
1 = Select falling edge as interrupt trigger event
6.6
Operation Guide
Port 0 to Port 3 are memory-mapped into the Data Memory addressing space. They are respectively mapped into
80h, 90h, A0h and B0h registers for ports P0, P1, P2 and P3. Writing to a port data register sets the voltage levels of
the corresponding port pins that have been configured to operate as outputs. Reading from a data register reads the
voltage levels of the corresponding port pins.
As illustrated in Figure 8-1, there are major differences reading the port values when the port is set as input and
output. When the port is set as output, the CPU will read the port value from Px register instead of the port pin value.
When the port is set as input, the CPU will read the value from port pin directly instead of the port value from Px
register. As a result, the user should be very careful when using Read-then-Write instructions to access the ports
and change PxDIR before write the output value to Px when using port as output. For example:
Code assembler:
ANL P0DIR, #0FEH
MOV P0, #01h
Code C51:
P0DIR &= 0Xfe;
P0 = 0x01;
The first instruction in this example configures P00 as output, and then the second instruction writes the Port 0 data
register (P0), which controls the output levels of the Port 0 pins, P00 through P07. Figure 8-1 shows the internal
hardware structure and configuration registers for each pin of Port 0~3.
