APPOTECH CW6632B, Руководство пользователя

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3 CPU Core Information 17
CW6632B Bluetooth 3.0 Audio Player SOC Version 1.0.0
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MOVX A, @DPTR
MOVX @DPTR, A
INC DPTR
MOV DPTR, #data16
The CW6632B also offers a programmable option that automatically increases (or decreases) the contents of the
selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or
decrement) is dependent on the setting of the DPAID bits. This option is enabled by setting the automatic
increment/decrement enable (DPAID: DPCON.3) to a logic 1 and is affected by one of the following 3 DPTR-related
instructions.
DPTR-related instructions are:
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
Register 3-6 SP
– Stack Pointer Low Byte
Position 7 6 5 4 3 2 1 0
Name SP
Default 0 0 0 0 0 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
Register 3-7 SPH
– Stack Pointer High Byte
Position 7 6 5 4 3 2 1 0
Name SPH
Default 0 0 1 1 1 1 1 1
Access R/W R/W R/W R/W R/W R/W R/W R/W
In a standard 8051, there is only an 8-bit stack pointer (SP). It can only use the internal 256 byte data memory as
stack memory. To increase the stack space for more complex application, CW6632B supports a 16-bit extend stack
pointer, it can use both internal data RAM and the 20K byte on-chip SRAM as stack memory. There are 2 registers
for stack control.
Register 3-8 PSW
– Processor Status Word
Position 7 6 5 4 3 2 1 0
Name CY AC EC RS1 RS0 OV EZ P
Default 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
CY : Carry Flag
AC : Auxiliary carry flag
EC: Extern instruction Carry flag
RS1 , RS0 : Register bank select
00 = bank0
01 = bank1