Apollo TI6VGA, Руководство пользователя

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Chapter 6 BIOS Configuration
36 TI6VGA User’s Manual
6.5 Chipset Features Setup
This Setup menu controls the configuration of the motherboard chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
Bank 0/1 DRAM Timing
:
SDRAM 10ns CPU Warning Temperature : 66
°
C/151
°
F
Bank 2/3 DRAM Timing
:
SDRAM 10ns Current System Temp. : 27
°
C/ 80
°
F
Bank 4/5 DRAM Timing
:
SDRAM 10ns Current CPU/Chips Temp. : 33
°
C/ 91
°
F
SDRAM Cycle Length : 3 Current CPU FAN Speed : 3879 RPM
Memory Hole At 15MB Addr : Disabled Current chassis FAN Speed : 0 RPM
Read Around Write Disabled VCCP : 2.00v VTT(V) : 1.50v
Concurrent PCI/Host
:
Enabled VCC3 : 3.28v + 5v : 4.99v
Video RAM Cacheable
:
E12V : 12.03V -12V : -11.59v
AGP Aperture Size (MB)
:
64 -5v : -5.12v
CPU Clock Multiplier : 3.5 Shutdown Temperature :: 75
°
C/167
°
F
CPU/PCI Clock Select : Default
OnChip USB : Enabled
USB Keyboard Support
:
Disabled
Auto Detect DIMM/PCI Clk
:
Disabled
Spread Spectrum
:
Disabled
ESC : Quit
Ç È Æ Å
: Select Item
F1 : Help PU/PD/+/- : Modify
F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is
3 .
Memory Hole at 15MB Addr.
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to 16MB
memory address space to ISA expansion cards. This makes memory from
15MB and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to
Disabled.
Read Around Write
DRAM optimization feature: If a memory read is addressed to a location
whose latest write is being held in a buffer before being written to
memory, the read is satisfied through the buffer contents, and the read is
not sent to the DRAM. The default setting is
Enabled .