Page 48
MICROPHONE PREAMPLIFIER
Page 49
Instruction Manual
APPENDIX F
not terminated in its characteristic impedance. In most cas-
es, unmatched word clock lines are driven by a low output
impedance voltage driver and loaded by a high impedance
receiver.
A length of coax driven by a brute forced output driver will
cause edge ringing and wave distortion of the clock pulses.
If the length is too long, the distortion can cause clock jitter.
It is important to minimize the cable length.
Brute Force Clocking
It is an unfortunate fact that transmission line techniques
for word clock have not been implemented in much of
the digital audio equipment presently available. This leads
to real clocking compatibility problems in today’s studios.
Obvious problems are usually seen as “no lock” but less
obvious is sound degrading jitter.
Though ugly from an engineering viewpoint, the only solu-
tion is such cases is to apply unmatched transmission lines
as best as one can and then rely on “brute force” clocking
to hold it all together.
With brute force clocking, 5Vp-p clock pulses are fed out
from a low impedance line driver with no intention of
impedance matching the coaxial cable. Daisy chaining is
not usually possible because the magnitude of jitter rapidly
rises. Very short cable runs are necessary. Every piece of
gear gets a separately driven feed, and no terminating load
is used.
Figure 4 above illustrates the Brute Force clock principle. We
have found that many of the commercially available clock
detangler and regenerator/driver boxes actually source out
brute force clock as their hedge against unknown studio
equipment characteristics.
Clocking The 1788A With 75
Ω
Matched Lines
First, you need to be aware that when switched to the
external clock mode, the 1788A automatically connects the
word clock input jack to the word clock output jack through
a metal relay contact. This permits direct feed-through of
clock with almost no loading from the 1788A. If using a
75
Ω
clock system, then you can daisy-chain the W.C. input
to additional 1788A’s or other equipment. If the 1788A is
Input Jack
Loop-Through Jack
Input Jack
75
Ω
Coax Feed
75
Ω
Coax
75
Ω
Coax
Loop-Through Jack
Hi-Z Clock Receiver
Hi-Z Clock Receiver
Hi-Z Clock Receiver
First
Device
N
Devices
Last
Device
Input Jack
75
Ω
Load
Adapter
Loop-Through Jack
Figure 3
Transmission Daisy-Chain
5Vp-p Output Level
Open Circuit
Still 5Vp-p But With Ringing
(Worse With Longer Cable)
Coax
Line
Brute Force
Clock Transmitter
Brute Force
Clock Transmitter
Clock Receiver
<10
Ω
Source
Impedance
<10
Ω
Source
Impedance
Figure 4
Principle of Unmatched Lines
And Brute Force Clocking
