
FPGA Discovery-III XC3S200 Board Manual V1.0 (REV5, 9/3/2007)
12
(a) (b)
1F:4AG 14 JEH0C?B69B1J?070BJ2]>J[0`AJ1;9F5 TTL T1d0 CMOS 7VMB9E/0^8]>JV06 FPGA
4.3) E:SH39DEF7EIQ];]MEF
a) 5=:9`QK]9:]?MTEU]87
4B63MB80^8]>J/0123435068Aa@A<H^J`293J^3:5?0C3E/ ( Push button switch ) 0CF? 5 JEH=d0 PB1 | PB5 J?00CF?9E/VBV06
FPGA X3C4SB6B8D// Active low =d0TB9[@?@A9B193:>@I;7:i850I^9 }1~ D5;7@dG093:>@I;7:i850I^9 }0~ 78dG06IB9@AJEHJMB84B8
RNET1 J?0]F50E]0CF?3E61F:4AG 15
1F:4AG 15 <H^J`293J^3:5?0C3E/
b) ]:H5=:9GQ
3^]<H^JL2 (Dip Switch) /8/0123435068Aa@A 8 <H^JL2 X3C:9J^4SB6B8D// Active low =d0 TB975dG08<H^J`256[:4AG OFF
I;4SBKTM[3M50I^9 }1~ D5;TB975dG08<H^J`2V_a8[:4AG ON I;4SBKTM[3M50I^9 }0~ 78dG06IB9@AJEHJMB84B8 RNET2 J?0]F50E]0CF?3E61F:4AG 16