99
A
A
X
X
4
4
L
L
/
/
A
A
X
X
4
4
L
L
-
-
N
N
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
D
D
I
I
M
M
M
M
(
(
D
D
u
u
a
a
l
l
I
I
n
n
L
L
i
i
n
n
e
e
M
M
e
e
m
m
o
o
r
r
y
y
M
M
o
o
d
d
u
u
l
l
e
e
)
)
DIMM socket has total 168-pin and supports 64-bit data. It can be single or double side, the golden finger signals on each side
of PCB are different, and that is why it was called Dual In Line. Almost all DIMMs are made by
, which operate at 3.3V.
Note that some old DIMMs are made by FPM/
and only operate at 5V. Do not confuse them with SDRAM DIMM.
D
D
M
M
A
A
(
(
D
D
i
i
r
r
e
e
c
c
t
t
M
M
e
e
m
m
o
o
r
r
y
y
A
A
c
c
c
c
e
e
s
s
s
s
)
)
ices.
mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
ility to detect double-bit error and automatically correct single-bit error while
a
a
O
O
u
u
t
t
p
p
u
u
t
t
)
)
M
M
e
e
m
m
o
o
r
r
y
y
FPM (Fast Page Mode). Unlike traditional FPM that tri-states the memory
M holds the memory data valid until the next memory access cycle, that is
Channel for communications between the memory and surrounding dev
E
E
C
C
C
C
(
(
E
E
r
r
r
r
o
o
r
r
C
C
h
h
e
e
c
c
k
k
i
i
n
n
g
g
a
a
n
n
d
d
C
C
o
o
r
r
r
r
e
e
c
c
t
t
i
i
o
o
n
n
)
)
The ECC
special algorithm. The ECC algorithm has the ab
parity mode can only detect single-bit error.
O
(
(
E
E
x
x
t
t
e
e
n
n
d
d
e
e
d
d
D
D
a
a
t
t
The EDO DRAM technology is actually very similar to
output data to start the pre-charge activity, EDO DRA
similar to pipeline effect and reduces one clock state.
