113
A
A
X
X
4
4
G
G
P
P
r
r
o
o
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
S
S
D
D
R
R
A
A
M
M
(
(
S
S
y
y
n
n
c
c
h
h
r
r
o
o
n
n
o
o
u
u
s
s
D
D
R
R
A
A
M
M
)
)
chnologies that allow DRAM to use the same clock as the CPU host bus (
EDO
SDRAM is one of the DRAM te
and FPM are
clock signal). It is similar as
PBSRAM
asynchronous and do not have
to use burst mode transfer. SDRAM comes in 64-bit
168-pin
DIMM
and operates at 3.3V. AOpen is the first company to support dual-SDRAM DIMMs onboard (AP5V), from Q1 1996
S
S
h
h
a
a
d
d
o
o
w
w
E
E
2
2
P
P
R
R
O
O
M
M
E
2
PROM operation, AOpen motherboard uses Shadow E
2
PROM for jumper-less and
n
n
g
g
l
l
e
e
I
I
n
n
L
L
i
i
n
n
e
e
M
M
e
e
m
m
o
o
r
r
y
y
M
M
o
o
d
d
u
u
l
l
e
e
)
)
single side. The golden finger signals on each side of PCB are identical. That is why it
de by FPM or
EDO
A memory space in Flash-ROM to simulate
battery-less design
S
S
I
I
M
M
M
M
(
(
S
S
i
i
SIMM socket is only 72-pin, and is only
was called Single In Line. SIMM is ma
DRAM and supports 32-bit data. SIMM had been phased out on
for component communication (especially for semiconductor IC).
otherboard. The data transfer rate of SMBus is only 100Kbit/s, it
current motherboard design.
S
S
M
M
B
B
u
u
s
s
(
(
S
S
y
y
s
s
t
t
e
e
m
m
M
M
a
a
n
n
a
a
g
g
e
e
m
m
e
e
n
n
t
t
B
B
u
u
s
s
)
)
SMBus is also called I2C bus. It is a two-wire bus developed
For example, set clock of clock generator for jumper-less m
allows one host to communicate with CPU and many masters and slaves to send/receive message.