Anaren A1101R04C, Руководство пользователя

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Distributor of Anaren: Excellent Integrated System Limited
Datasheet of A1101R04C00GM - IC RADIO MOD 433MHZ CONN 24-LGA
Contact us: sales@integrated-circuit.com Website: www.integrated-circuit.com
Page 6 of 26 A1101R04C – User’s Manual
Release Date 02/20/12
1.1. Features
Features:

Frequency range: 433.05 – 434.79
MHz

Ultra small package size 9mm x 12mm
x 2.5mm

Impedance controlled multi-layer PCB

Shielded Package

1.8 to 3.6 V operation

SPI Interface

RoHS Compliant

LGA Footprint

Low Power Consumption

Regulatory compliance for ETSI

Digital RSSI output

Programmable channel filter bandwidth

Programmable output power up to +12
dBm

High sensitivity (–116 dBm at
0.6kBaud, 1% packet error rate)

Low current consumption (15.7 mA in
RX, 250 kBaud, input well above
sensitivity limit)

Separate 64-byte RX and TX data
FIFOs

Fast startup time: 240us from SLEEP
to Rx or Tx mode

Data Rate: 0.6 – 600 Kbit/Sec

Sleep state: 0.2uA

Idle State: 1.7mA
Benefits Summary:

Operating temperature -40 to +85C

100% RF Tested in production

Common footprint for all family
members

No RF engineering experience
necessary

Only requires a 2 layer PCB
implementation

Excellent receiver selectivity and
blocking Performance

Suitable for frequency hopping and
multichannel systems due to a fast
settling frequency synthesizer with 75
us settling time

Suited for systems compliant with EN
300 220

No regulatory “Intentional radiator”
testing is required to integrate module
into end product. Simple certification
labeling replaces testing.
1.2. Theory of Operation
The A1101R04C is designed for low power wireless applications in the European band of
433.05 MHz to 434.79 MHz. It can be used to implement a variety of networks, including point
to point, point to multipoint, peer to peer and mesh networks.
The A1101R04C interfaces to an application microcontroller via an SPI bus. Physical and MAC
layer functionality are accessed via the SPI bus, through addressable registers as well as
execution commands. Data received or to be transmitted are also accessed through the SPI bus
and are implemented as a FIFO register (64 bytes each for Tx and Rx).
To transmit, a frame of data is placed in the FIFO; this may include a destination address. A
transmit command is given, which will transmit the data according to the initial setup of the
registers. To receive data, a receive command is given, which enables the unit to “listen” for a
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