DEMO MANUAL SCP-LT8362-S-EVALZ
Rev. 0
3
CONFIGURATION SETTINGS
Demonstration circuit SCP-LT8362-S-EVALZ features the
LT8362 in a SEPIC configuration. It operates with a switch-
ing frequency of 2MHz and has an output voltage of 12V.
The output of the SCP-LT8362-B-EVALZ is resistor-pro-
grammable from 5V to 48V. The board can be also config-
ured to drive VIOC-capable LDO regulators.
OUTPUT VOLTAGE PROGRAMMING
Table 2.
Resistor Selection Guide for Common Output Voltages
V
OUT
(V)
R6 (
Ω
)
R8 (
Ω
)
5.0
24.3K
11.5K
6.0
31.6K
11.5K
7.0
115K
34.0K
8.0
102K
25.5K
9.0
118K
25.5K
10.0
105K
20.0K
11.0
107K
18.2K
12.0
71.5K
11.0K
13.0
97.6K
13.7K
14.0
78.7K
10.2K
15.0
115K
13.7K
16.0
102K
11.3K
17.0
162K
16.9K
18.0
205K
20.0K
19.0
150K
13.7K
20.0
115K
10.0K
21.0
243K
20.0K
22.0
255K
20.0K
23.0
226K
16.9K
24.0
140K
10.0K
25.0
215K
14.7K
30.0
442K
24.9K
35.0
287K
13.7K
40.0
255K
10.7K
45.0
374K
13.7K
48.0
309K
10.7K
EN/UVLO PIN CONFIGURATION
The EN/UVLO pin is tied to the optional SCP Run/Se-
quence header P1. To create a harness for this function,
use Molex part # 0510650300 with crimp pin # 50212-
8000.
To use an active run signal, use a 1.00M for either pull-up
or pull-down resistors R1 and R3, short R13 with 0
W
, and
use the drive signal from connector P1.
If precision UVLO operation is desired, program enable di-
vider R5 and R6 such that:
The LT8330 has an accurate 1.60V threshold which places
the part into under voltage lockout. The hysteresis thresh-
old on the rising edge is typically 80mV and scales by the
factor:
VOLTAGE INPUT-TO-OUTPUT CONTROL (VIOC)
IMPLEMENTATION
To implement the VIOC function for this regulator, set R27
to 0
W
. Refer to the “Configuration Settings” section in the
Demo Manual for the LDO board and use the following
configuration for this board.
Table 3.
VIOC Cross-Reference Designators
VIOC SETTING REFERENCES
R
BOT
R
TOP
R
MAX
V
OUT
Reference Designators
R8
R6
R14
I
SINK
is the current through R
MAX
, typically 15µA, so R
BOT
should be sized such that the divider current runs a mini-
mum of 100µA to minimize the I
SINK
error term.
V
OUT
=
1 .6 V
FBX
1
+
R6
R8
⎛
⎝⎜
⎞
⎠⎟
R6
=
1 0 k
−
1 0 0 k,
nominal
R5
=
R6
V
IN
−
1 .6 0 V
TH
1 .6 0 V
TH
⎛
⎝⎜
⎞
⎠⎟
V
HYST
=
80mV
R5
+
R6
R6
⎛
⎝⎜
⎞
⎠⎟
V
L DOIN
−
V
L DOOUT
=
V
VIOC
=
1 .6 0 V
FB
R
BOT
+
R
TOP
R
BOT
⎛
⎝⎜
⎞
⎠⎟
V
MAX
(
)
LDOIN
=
1 .6 0 V
FB
R
BOT
+
R
TOP
+
R
MAX
R
BOT
⎛
⎝⎜
⎞
⎠⎟
+
I
SINK
R
MAX
