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EVAL-SSM4567Z User Guide

UG-704

Rev. 0 | Page 17 of 23

Figure 24. Evaluation Board Layout, Power Plane (Layer 3)

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Содержание EVAL-SSM4567Z

Страница 1: ...nes an audio digital to analog converter DAC a power amplifier and PDM or PCM I2 S TDM digital audio interfaces on a single chip Using the SSM4567 audio can be transmitted digitally to the audio amplifier significantly reducing the effect of noise sources on the transmitted audio and eliminating the need for input coupling capacitors The SSM4567 is capable of delivering 2 5 W of continuous output ...

Страница 2: ...e Output Signals 5 PDM Control Mode 6 PDM Channel Selection 6 PCM Mode Pin Setup and Control 6 Evaluation Board Software Quick Start Procedures 7 Hardware Only Quick Start 7 SSM4567 Control Software Setup 7 SSM4567 USB Driver Installation 7 Software Instructions 7 Passive Component Selection 10 Output Ferrite Beads FB5 to FB6 10 Output Shunting Capacitors C26 AND C27 10 Evaluation Board Schematics...

Страница 3: ...Figure 2 shows the typical bench characterization setup used to evaluate the audio performance of the SSM4567 See the Evaluation Board Software Quick Start Procedures section to get started Figure 1 Evaluation Board Overview Figure 2 Default Quick Start Setup SSM4567 DC POWER INPUTS OPTICAL SPDIF INPUT I2S PDM DIGITAL AUDIO INPUT AND THRU CONNECTOR I2C COMMS CONNECTOR SPDIF RESET SW SPEAKER OUTPUT...

Страница 4: ...rs to translate the signals to 1 8 V levels Figure 3 Power Input Terminals and Default Jumper Settings VBAT Only Using Internal Regulators for IOVDD and 3 3 V INPUT SIGNALS On the right side of the PCB are two 10 pin headers J25 and J26 One header is used to connect the digital input audio signals to the amplifier and the other can be used to connect to other EVAL SSM4567Z boards to enable the tes...

Страница 5: ...ternal level can be injected using Pin 2 of J19 Note that Pin 3 of J19 is not connected to any signals on the board NC The input of the level shifter is selected using J29 Installing a jumper on Pin 1 and Pin 2 connects the SDATAO signal to the level shifter The output of the level shifter appears on J15 Pin 1 is the shifted SDATAO signal and Pin 2 is ground When not using the level shifter it is ...

Страница 6: ...on Descriptions Device Setting LR_SEL ADDR Pin Configuration Right Channel Select High IOVDD Left Channel Select Low GND PCM MODE PIN SETUP AND CONTROL When the SEL pin is tied to IOVDD the SSM4567 is set for PCM mode operation In this mode the SSM4567 supports standalone operation I2 C control or control using commands sent over the input serial audio TDM interface See Figure 9 for the location o...

Страница 7: ...e Skip this procedure if you previously installed any SigmaStudio or USBi related drivers from Analog Devices Ensure that the Cypress CYUSB USB driver is installed during the SigmaStudio installation If you need to verify installation you can find the driver on your computer in this location C Program Files Analog Devices SigmaStudio x x USB drivers x86 or x64 dpinst exe Note that the parentheses ...

Страница 8: ...SM4567 dll to C Program Files Analog Devices SigmaStudio 3 7 b From the main SigmaStudio window click Tools Add Ins Browser Add Dll and browse to locate the SSM4567 dll you copied to in Step 5a and then click Save This loads the SSM4567 as a processor in SigmaStudio Figure 15 Adding a Processor DLL Using the AddIns Tool c From the main SigmaStudio window click File New Project to start a new GUI p...

Страница 9: ...EVAL SSM4567Z User Guide UG 704 Rev 0 Page 9 of 23 Figure 17 SSM4567 Evaluation Software GUI 12378 018 ...

Страница 10: ...420 mA and impedance at 100 MHz must be 120 Ω In addition the lower the dc resistance DCR of these beads the better for minimizing their power consumption Table 4 describes suggested beads Table 4 Suggested Output Beads Part No Manufacturer Z Ω IMAX mA DCR Ω Size mm BLM18PG121SN1D Murata 120 2000 0 05 1 6 0 8 0 8 MPZ1608S101A TDK 100 3000 0 03 1 6 0 8 0 8 MPZ1608S221A TDK 220 2000 0 05 1 6 0 8 0 8...

Страница 11: ...33R SDATA_SPDIF LRCLK_SPDIF MCLK_SPDIF BCLK_SPDIF VL U2 TORX147 OUT 1 GND 2 VCC 3 U3 12 288MHZ 3 State 1 GND 2 OUT 3 VDD 4 FB3 600 OHM FB4 600 OHM FB2 600 OHM S1 FSM6JSMA 1 4 2 3 U1 CS8416 CZZ RXP3 1 RXP2 2 RXP1 3 RXP0 4 RXN 5 VA 6 AGND 7 FILT 8 RST 9 RXSEL1 10 RXSEL0 11 TXSEL1 12 TXSEL0 13 NV RERR 14 AUDIO 15 96KHZ 16 RCBL 17 U 18 C 19 TX 20 VL 21 DGND 22 VD 23 RMCK 24 OMCK 25 SDOUT 26 OSCLK 27 O...

Страница 12: ...1V8_REG J2 1 J5 1 EXT_IOVDD TP8 1 TP9 1 IOVDD TP10 1 J4 1 TP11 1 U5 ADP1711A UJZ 1 8 R7 IN 1 GND 2 EN 3 BYP 4 OUT 5 U4 ADP1711A UJZ 3 3 R7 IN 1 GND 2 EN 3 BYP 4 OUT 5 R21 470R C14 0 01uF 50V C13 10uF 10V C12 1uF 16V 3V3_REG C11 1uF 16V J7 1 2 C16 10uF 10V C19 0 01uF 50V C15 1uF 16V TP3 1 TP2 1 TP4 1 TP5 1 TP6 1 TP7 1 C18 1uF 16V VDD_REG IOVDD 1V8_REG J23 1 2 3V3_REG 12378 020 ...

Страница 13: ...TN D4 OUTP E2 VBST C3 VBAT E3 SDA E4 ADDR B1 SEL B2 VBST C4 BSTSW A4 BSTSW B4 IOVDD A1 IOVDD OUTN OUTP FSYNC L1 1uH 4 7uH TP12 1 C24 22uF 10V TP13 1 BCLK TP14 1 SDATAI C20 10uF 10V C21 1uF 16V VBAT BSTSW SDATAO SDATAO IOVDD J9 1 2 3 FB5 220 OHM FB6 220 OHM C26 510p F 50V NC C27 510p F 50V NC C23 0 1uF 50V BCLK FSYNC SDATAI J12 1 2 3 C22 1uF 16V J10 CON2 1 2 R39 100K 5VDD_USB IOVDD VBAT C25 1uF 16V...

Страница 14: ...F T_LEVEL J 16 H EA D ER 6X2 1 2 3 4 5 6 7 8 9 10 11 12 BC LK SD ATAO SD ATAO I2S LRCK TDM BCLK PDMCLK I2S SDATA TDM SDATA PDMDAT SDATAO I2S BCLK TDM FSYNC I2S LRCK TDM BCLK PDMCLK SDATAO I2S BCLK TDM FSYNC I2S SDATA TDM SDATA PDMDAT J 27 1 2 3 BC LK SD ATAO J 28 1 2 3 F SY N C 3V3_ R EG J 29 1 2 3 SD ATAO R 26 33R R 27 33R R 28 33R R 29 33R F SY NC _E XT1 SD ATAI _E XT1 U 7 F XLP34P5X VCC 1 1 A 2...

Страница 15: ...EVAL SSM4567Z User Guide UG 704 Rev 0 Page 15 of 23 Figure 22 Evaluation Board Layout Primary Side Layer 1 12378 023 ...

Страница 16: ...UG 704 EVAL SSM4567Z User Guide Rev 0 Page 16 of 23 Figure 23 Evaluation Board Layout Ground Plane Layer 2 12378 024 ...

Страница 17: ...EVAL SSM4567Z User Guide UG 704 Rev 0 Page 17 of 23 Figure 24 Evaluation Board Layout Power Plane Layer 3 12378 025 ...

Страница 18: ...UG 704 EVAL SSM4567Z User Guide Rev 0 Page 18 of 23 Figure 25 Evaluation Board Layout Secondary Side Layer 4 12378 026 ...

Страница 19: ...EVAL SSM4567Z User Guide UG 704 Rev 0 Page 19 of 23 Figure 26 Evaluation Board Layout Top Silkscreen 12378 027 ...

Страница 20: ...UG 704 EVAL SSM4567Z User Guide Rev 0 Page 20 of 23 Figure 27 Evaluation Board Layout Bottom Silkscreen 12378 028 ...

Страница 21: ... J3 J4 J5 Post binding grounded type nickel Johnson Emerson 111 2223 001 15 3 J14 J25 J26 Conn header 2 54 mm 10 POS gold Sullins Electronics Corp SBH11 PBPC D05 ST BK 16 1 J16 Conn header 100 dual str Sullins Electronics Corp PRPC040DAAN RC 17 1 L1 2 2 µH 1 85 A 20 Vishay Dale IFSC1008ABER2R2M01 18 4 FB1 FB2 FB3 FB4 Ferrite bead 600 Ω 0805 Taiyo Yuden BK2125HM601 T 19 2 FB5 FB6 RES 0 0 Ω 1 8 W 08...

Страница 22: ...Adjustable low dropout voltage regulator Analog Devices ADP1711AUJZ 1 8 R7 35 1 U1 192 kHz AES3 SPDIF receiver Cirrus Logic CS8416 CZZ 36 1 U4 Adjustable low dropout voltage regulator Analog Devices ADP1711AUJZ 3 3 R7 37 1 U3 Oscillator 12 288 MHz 3 3 V SMD Abracon Corp ASEP BLANK 38 1 U6 SSM4567 WLCSP Analog Devices SSM4567CBZ RL ...

Страница 23: ...e or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or an...

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