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EVAL-AD9888EB
Rev. 0 | Page 4 of 4
Table 1. Sample Settings for the EVAL-AD9888EB
PLL Timing Chart
Horizontal Sync
Mode Resolution
Nominal Frequency
(kHz) Polarity
PLL Divider
1
N + 1
Nominal Pixel
Clock (MHz) VCO
Range
2
Charge Pump
Current
2
VGA 640 × 480 @ 60 Hz 31.469 N 800 25.175 00 010
640 × 480 @ 72 Hz 37.861 N 832 31.500 00 100
640 × 480 @ 75 Hz 37.500 N 840 31.500 00 100
640 × 480 @ 85 Hz 43.269 N 832 36.000 00 100
SVGA 800 × 600 @ 56 Hz 35.156 N/P 1024 36.000 00 100
800 × 600 @ 60 Hz 37.879 P 1056 40.000 00 101
800 × 600 @ 72 Hz 48.077 P 1040 50.000 01 011
800 × 600 @ 75 Hz 46.875 P 1056 49.500 01 011
800 × 600 @ 85 Hz 53.674 P 1048 56.250 01 011
XGA 1024 × 768 @ 60 Hz 48.363 N 1344 65.000 01 100
1024 × 768 @ 70 Hz 56.476 N 1328 75.000 01 100
1024 × 768 @ 75 Hz 60.023 P 1312 78.750 01 101
1024 × 768 @ 80 Hz 64.000 P 1336 85.500 10 011
1024 × 768 @ 85 Hz 68.677 P 1376 94.50 10 011
SXGA 1280 × 1024 @ 60 Hz 60.020 P 1688 108.000 10 011
1280 × 1024 @ 75 Hz 80.000 P 1688 135.000 10 100
1280 × 1024 @ 85 Hz 91.100 P 1730 157.500 11 100
UXGA 1280 × 1024 @ 60 Hz 75.000 P 2160 162.000 11 100
1280 × 1024 @ 65 Hz 81.300 P 2160 175.500 11 100
1280 × 1024 @ 70 Hz 87.500 P 2160 189.000 11 101
1280 × 1024 @ 75 Hz 93.800 P 2160 202.500 11 101
1
PLL divisor to the chip should be an odd integer; Chip divide ratio = Input N + offset of 1.
2
The VCO range and charge pump current settings are preliminary and may need slight adjustments.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
Model Package Description
AD9888/PCB Evaluation Board
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C04329–0–7/03(0)