EVAL-AD9888EB
Clamp and Hsync Out Settings
Clamp Placement, Clamp Duration, and Hsync Out Width
controls are contained in Registers 05h to 07h and can be
changed bit-by-bit, by setting a value for the registers (decimal
value), or by moving the control bar right or left to increase or
decrease the value. When changing the value using one of these
methods, the change is reflected in the other two. Again, unless
the Load Register On Change box is checked, these value
changes are not loaded into the AD9888 until the Load button is
clicked. Note that Clamp Placement values of 1, 2, 4, 8, 16, 32,
64, and 128 are not supported.
Gain and Offset Settings
Gain for the red, green, and blue video channels is controlled via
all eight bits of Registers 08h to 0Ah and can be changed bit-by-
bit, by setting a value for the registers (decimal value), or by
moving the control bar right or left to increase or decrease the
value. The 7-bit offset control for the red, green, and blue
channels is contained in Registers 0Bh to 0Dh. These can be set
in the same manner as gain, with the additional option of
setting the 7-bit decimal value. Note that using the gain and
offset control bars will change all three channels by the same
amount, regardless of their setting. For example, if, in order to
achieve color balance, the offset settings are 60, 70, and 80 for R,
G, and B, respectively, the minimum settings are 0, 10, and 20.
The maximum offset settings would then be 107, 117, and 127.
Note that for the purpose of having the cleanest placement and
routing of the analog inputs, the EVAL-AD9888EB’s red and
blue inputs are reversed. In other words, the red analog data is
routed through the AD9888’s blue channel and vice versa.
Therefore, if a blue offset and gain adjustment is desired, the
registers for the red channel should be modified.
Sync Control
Register 0Eh contains bits for controlling input and output
Hsync and Vsync signals. The user can toggle each bit by
clicking on it. The resulting state of a bit is reflected in the box
to the right of that bit. Refer to the AD9888 Data Sheet for a
functional description of these bits.
Clamp, Coast, and Power Management
Register 0Fh contains bits for controlling the Clamp and Coast
functions, as well as Power Management functions. The user
can toggle each bit by clicking on it. The resulting state of the
bits is reflected in the box to the right of each bit. Refer to the
AD9888 Data Sheet for a functional description of these bits.
SOG and Clamp Control
Register 10h contains bits for controlling the SOG threshold
and Clamp selection functions. Register 11h contains bits for
adjusting the Sync separator threshold. The 5-bit (Reg 10h7:3)
SOG Threshold can be modified bit-by-bit, by changing the
5-bit (decimal) value, or by sliding the control bar. The user can
toggle each Clamp selection bit by clicking on it. The resulting
state of the bits is reflected in the box to the right of each bit.
The Sync separator threshold can be changed bit-by-bit, by
setting a value for the register (decimal value), or by moving the
control bar right or left to increase or decrease the value. See the
AD9888 Data Sheet for a functional description of these bits.
Pre-Coast and Post-Coast
Registers 12h and 13h contain the bits for controlling Pre-Coast
and Post-Coast. The 8-bit Pre-Coast and 8-bit Post-Coast can
be modified bit-by-bit, by changing the 8-bit (decimal) value, or
by sliding the control bar. The resolution of this adjustment,
which applies to the AD9888’s internal Coast function and does
not alter external Coast signals, is in Hsync periods. See the
AD9888 Data Sheet for a functional description of these bits.
Sync and Coast Status (Read-Only)
Register 14h is a read-only register that provides status for
Hsync, Vsync, SOG, and Coast polarity. Performing a read (by
clicking the Read button) allows the user to see the status of
each of these bits. The status is also reflected in the text to the
right of each of these bits. See the AD9888 Data Sheet for a
functional description of these bits.
Input/Output Modes
Register 15h contains bits for controlling input and output
modes. These include output formatting, input select, and
bandwidth control. The user can toggle each bit by clicking on
it. The resulting state of the bits is reflected in the box to the
right of each bit. See the AD9888 Data Sheet for a functional
description of these bits.
OTHER SOFTWARE FEATURES
PLL Divider Calculator
The AD9888 register setup software includes a calculator that
computes the PLLDIV setting. Simply click the Calculator
button at the bottom left side of the window and enter the pixel
clock and Hsync frequencies.
SCHEMATICS AND LAYOUT
The schematics and layout for this board are included in
separate files. They can be found on the CD-ROM.
CONTACT INFORMATION
If you have questions or would like more information, email us
directly at [email protected], visit our website at
http://www.analog.com/flatpanel
, or call the Analog Devices
help line at 1-800-AnalogD (1-800-262-5643).
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