Analog Devices EVAL-AD7492SDZ, Руководство пользователя, Страница: 5 / 24

EVAL-AD7492SDZ User Guide UG-371
Rev. 0 | Page 5 of 24
Table 2. Link Options—Setup Condition
Link No. Position Function
LK1 A V
DRIVE
is set to AV
DD
.
LK2 B
The CONVST signal is provided by the EVAL-SDP-CB1Z .
LK3 A The REFOUT pin of the AD7492 is connected to the bias circuitry.
LK6 A
The RD signal is provided by the EVAL-SDP-CB1Z .
LK8 A
The CS signal is provided by the EVAL-SDP-CB1Z .
LK9 Inserted The buffered REF OUT voltage is divided by a factor of 3, and it is used as the bias input for U6.
LK10 B The V
IN
pin of AD7492 is connected to the buffered unipolar signal input that is applied to SK1.
LK14 B The AD7492 goes into partial sleep mode if low power operation is selected.
LK15 Inserted The unipolar V
IN
impedance matching resistor is connected into the circuit.
LK20 A The buffered internal reference is used as the bias input for U6.
LK801 A It selects the VSS_−5V signal generated on the board as opposed to the externally connected VSS (J800-1) signal.
LK802 A It selects the VDD_+5V signal generated on the board as opposed to the externally connected VDD (J800-3) signal.
LK701 A It selects the AV
DD
signal generated on the board as opposed to being externally connected via J703.
POWER SUPPLIES
Take care before applying power and signals to the evaluation
board to ensure that all link positions are as required by the
operating mode.
When using the
EVAL-AD7492SDZ in conjunction with the
EVAL-SDP-CB1Z board, connect the dc transformer to the J700
connector. AV
DD
, DV
DD
, and V
DRIVE
are generated on-board. Each
supply is decoupled on the EVAL-AD7492SDZ using 10 µF and
0.1 µF capacitors. A single ground plane is used on this board to
minimize the effect of high frequency noise interference.
Table 3. External Power Supply Required
Power
Supply
Terminal Voltage
Range (V)
Purpose
V
IN
1
+7 to +9 Supplies all the on-board power
supplies that generate all the
required supplies to run the
evaluation board
V
DD
+5.5 AmpVDD
V
SS
−5.5 Amplifier −VSS
AV
DD
2 +2.7 to +5.25 ADC analog and digital supply
rails
V
DRIVE
+2.7 to +5.25 Supply voltage for the output
drivers and digital input circuitry
1
When this is supplied, all other power supplies are available on-board. If this
supply is not used, all other supplies must be sourced from an external
source.
2
Analog supply voltage. This is the only supply voltage for all the analog
circuitry on the AD7492 . The AV
DD
and DV
DD
voltages should ideally be at the
same potential and must not be more than 0.3 V apart, even on a transient
basis. Decouple this supply to AGND.
PARALLEL INTERFACE
The EVAL-AD7492SDZ communicates with the EVAL-SDP-CB1Z
board using level shifters. The EVAL-SDP-CB1Z operates at a
3.3 V logic level. This allows V
DRIVE
voltages to exceed 3.3 V. An
external CONVST signal can be supplied to the board via the SK2
SMB. Parallel data can only be monitored via the
EVAL-SDP-CB1Z
board and software. A break out board ADZS-BRKOUT-EX3 is
available that allows access to the digital lines.