Analog Devices EVAL-AD5693RSDZ, Руководство пользователя

Страница: 8 / 12

UG-675 EVAL-AD5693RSDZ User Guide
Rev. A | Page 8 of 12
EVALUATION BOARD SCHEMATICS AND ARTWORK
PL
EA
SE L
A
B
EL
T
P A
S PER
T
H
E N
ET
I
T
I
S C
O
N
N
EC
T
ED
T
O
PL
EA
SE L
A
B
EL
T
P A
S PER
T
HE
NE
T
I
T
I
S
CO
NNE
CT
E
D T
O
P
M
O
D CO
NNE
CT
O
R
n
a
n
o
DAC+
ANAL
O
G
S
UP
P
L
Y
RE
F
E
RE
NCE
DI
G
IT
AL
S
UP
P
L
Y
CO
NNE
CT
O
NL
Y
I
F
T
HE
S
DP
I
S
NO
T
CO
NNE
CT
E
D
L
ABE
L
S
:
EXT
R
E
F
192
ADR4
3
1
L
ABE
L
S
:
3
V3
5V
V_
EXT
C8
0.
1µ
F
+
C7 10µ
F
±
20%
1
VI
N
2
G
ND
3
EN
5
V
O
UT
4
NC
U5
ADP
1
2
1
C4
1µ
F
C5
1µF
6
O
UT
P
UT
2
VS
3
SL
EEP
4
G
ND
U3
R
E
F
192
8
S
DA
6
A0
7
S
CL
4
L
DAC
10
V
O
UT
2
V
L
OGIC
3
R
ESET
1
V
DD
9 VR
EF
5
G
ND
U1
A
D
5693R
C1
0
0.
1µ
F
+
C9
10µ
F
±
20%
T
P6
T
P9
T
P3
T
P1
T
P2
R12
DNP
V
O
UT
T
P4
C6
DNP
EXT
_
R
EF
J2-
1
J2-
2
2
+
VI
N
4
G
ND
5
T
RI
M
7
CO
M
P
6
V
O
UT
U8
ADR4
3
1
BRZ
J5-
1
J5-
2
J5-
3
J5-
4
J5-
5
J5-
6
J5-
7
J5-
8
J5-
9
J5-
10
J5-
11
J5-
12
C1 0.
1µ
F
+
C2
10µ
F
±
20%
A
B C
A1
1
A
B C
A1
L
INK
L
DAC
R
ESET
S
Y
NC/
S
CL
S
CL
K/
A0
S
DI
N/
S
DA
V_
IO
VPO
S
VPO
S
+
5V
VPO
S
VR
EF
VR
EF
VPO
S
VR
EF
R
ESET
S
CL
K
SYN
C
S
DI
N
L
DAC
VPO
S
V_
IO
V_
IO
S
DA
S
CL
+
5V
+
5V
VPO
S
DG
ND
12145-006
Figure 7. EVAL-AD5693RSDZ Schematic—Power Supply and Signal Routes