Analog Devices dBCool ADT7476, Руководство пользователя

Страница: 5 / 72

ADT7476
Rev. B | Page 5 of 72
Parameter Min Typ Max Unit Test Conditions/Comments
Input Low Voltage, V
IL
0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
0.75 × V
CC
V
Input Low Voltage, V
IL
0.4 V
DIGITAL INPUT CURRENT
Input High Current, I
IH
±1 μA V
IN
= V
CC
Input Low Current, I
IL
±1 μA V
IN
= 0
Input Capacitance, C
IN
5 pF
SERIAL BUS TIMING 2 See Figure 2
Clock Frequency, f
SCLK
10 400 kHz
Glitch Immunity, t
SW
50 ns
Bus Free Time, t
BUF
4.7 μs
SCL Low Time, t
LOW
4.7 μs
SCL High Time, t
HIGH
4.0 50 μs
SCL, SDA Rise Time, t
r
1000 ns
SCL, SDA Fall Time, t
f
300 μs
Data Setup Time, t
SU;DAT
250 ns
Detect Clock Low Timeout, t
TIMEOUT
15 35 ms Can be disabled
1
All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are T
A
= 25°C and represent a most likely parametric norm. Logic inputs
accept input high voltages up to V
MAX
, even when the device is operating down to V
MIN
. Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge,
and V
IH
= 2.0 V for a rising edge.
2
SMBus timing specifications are guaranteed by design and are not production tested.
TIMING DIAGRAM
SCL
SDA
P S
S P
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
05382-002
Figure 2. Serial Bus Timing Diagram
www.BDTIC.com/ADI