ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 67 of 192
DMA CONTROLLER
DMA FEATURES
The DMA features are as follows:
•
14 dedicated and independent DMA channels
•
Two programmable priority levels for each DMA channel
•
Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.
•
Channels with lower number have highest priority. For example, SPI0 transmit has the highest priority; next highest is the
SPI0 receive.
•
Each DMA channel can access a primary and/or alternate channel control structure
•
Supports multiple DMA transfer types
•
Memory to memory
•
Memory to peripheral
•
Peripheral to memory
DMA OVERVIEW
Direct memory access (DMA) provides high speed data transfer between peripherals and memory. Data can be moved quickly by DMA
without any processor actions, which keeps processor resources free for other operations.
The DMA controller has 14 channels in total. The 14 channels used are dedicated to managing DMA requests from specific peripherals.
Channels are assigned as shown in Table 80.
Table 80. DMA Channel Assignment
Channel
Peripheral
0
SPI0 Tx
1
SPI0 Rx
2
SPI1 Tx
3
SPI1 Rx
4
UART Tx
5
UART Rx
6
I
2
C0 slave Tx
7
I
2
C0 slave Rx
8
I
2
C0 master
9
I
2
C1 slave Tx
10
I
2
C1 slave Rx
11
I
2
C1 master
12
ADC
13
Flash
The channels are connected to dedicated hardware DMA requests; a software trigger is also supported on each channel. This configuration
is done by software.
Each DMA channel has a programmable priority level: default or high. Within a priority level, arbitration is done using a fixed priority
that is determined by the DMA channel number. Channels with lower number have highest priority. For example, SPI0 transmit has the
highest priority; next highest is the SPI0 receive.
The DMA controller supports multiple DMA transfer data widths: independent source and destination transfer size (byte, half word, and
word). Source/destination addresses must be aligned on the data size.
The DMA controller supports peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfers and access to flash or
SRAM, as source and destination.
DMA OPERATION
The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M3 processor. The DMA request may
stall the processor access to the system bus for some bus cycles when the processor and DMA are targeting the same destination (memory
or peripheral).
