Analog Devices ADSP-TS201S EZ-KIT Lite, Руководство пользователя

Страница: 39 / 92

ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-3
ADSP-TS201S EZ-KIT Lite Hardware Reference
cessor core voltage is set to 1.05V. The internal DRAM is powered by an
external 1.5V regulator. Finally, the external interface (IO) operates at
2.5V but can accept up to 3.3V levels.
A 20 MHz SMT oscillator, in conjunction with a clock generator set to
5x, supply the input clock to the processors. The speed at which the core
operates is determined by pull-up and pull-down resistors on both the
clock generator (
U1
) and the
SCLKRAT2–0
bit of each of the processors. For
more information, see “Clock Mode Settings” on page 2-12 . By default,
the processor core runs at 500 MHz (20 MHz x 5 (
U1
) x 5 (
SCLKRAT
)
=500 MHz).
External Port
The external port (EP) connects to a 512K x 8-bit flash memory. The
flash memory connects to the boot memory select (
~BMS
) and memory
bank 0 (
~MS0
) pins. The flash can be used to boot the processor as well as
to store information during normal operation. Refer to “Flash Memory”
on page 1-9 for more information.
The EP also connects to a 4MB x 64-bit SDRAM. Refer to “SDRAM
Interface” on page 1-8 for more information.
Expansion Interface
The expansion interface consists of three connectors. The following table
shows the interfaces each connector provides. For the exact pinout of the
connectors, refer to
“Expansion Interface” on page B-11 .
Table 2-1. Expansion Interface Connectors
Connector Interfaces
J1
5V,
GND
, address, data