1
2
ON
1
2
ON
1
2
ON
8
1
2
4
5
6
7
ON
3
3.3V
3.3V
5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
DA_STANDALONE
DA_PWR
GND
VDD_EXT_DSP
DA_SOFT_RESET
RESET
D
4
3
2
1
A
B
C
20 Cotton Road
Nashua, NH 03063
A
B
C
D
4
3
2
1
PH: 1-800-ANALOGD
C
Title
Size
Board No.
Date
Sheet
of
DEVICES
ANALOG
Rev
ADSP-21479 EZ-BOARD
A0229-2009
0.1B
C1+
C1-
C2+
C2-
R1IN
R1OUT
R2IN
R2OUT
T1IN
T1OUT
T2IN
T2OUT
V+
V-
GND
NC1
NC2
NC3
RIN+
RIN-
ROUT
VCC
ACK
CLK
D0
D1
D2
D3
D4
D5
D6
D7
GND1
GND2
GND3
GND4
MSC1
MSC2
MSC3
MSC4
MSC5
MSC6
ACK
CLK
D0
D1
D2
D3
D4
D5
D6
D7
GND1
GND2
GND3
GND4
MSC1
MSC2
MSC3
MSC4
MSC5
MSC6
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
OFF
ON
OFF
ON
SW19.2
SW19.3
SW19.4
SW19.5
SW19.6
SW19.7
SW19.8
SW19.1
SN74LVC1G08
COAX
SPDIF
OUT
SN74LVC1G08
65LVDS2D
SPDIF
COAX
INPUT
ADM3202
"JTAG"
When designing your JTAG interface please refer to the
http://www.analog.com
JTAG SWITCHES
SW19.2
SW19.3
SW19.4
SW19.5
SW19.6
SW19.7
SW19.8
SW19.1
SWITCH
OFF
ON
OFF
ON
ON
ON
ON
VIA HP-USB EMUALTOR OR DEBUG AGENT (DEFAULT)
MULTI PROCESSOR JTAG SETTINGS VIA HP-USB EMUALTOR
REQUIRED FOR MORE THAN TWO BOARDS)
USING TWO OR MORE EZ-BOARDS (LINK PORT CABLES
SERIAL PORT
JP3 DEFAULT: ON
FOR TESTING PURPOSES ONLY
JP2 DEFAULT: OFF
FOR TESTING PURPOSES ONLY
JP4 DEFAULT: OFF
LOOPBACK HEADER
SINGLE PROCESSOR JTAG SETTINGS
ON
SWITCH
LOOPBACK HEADER
BOARD ATTACHED
TO EMULATOR
BOARD(S) NOT ATTACHED
TO EMULATOR
BOARD ATTACHED
TO EMULATOR
JTAG IN
JTAG OUT
All debug agent interface circuitry is considered
Engineer to Engineer Note EE-68 which can be found at
proprietary and has been omitted from this schematic.
SW20.1
ON
OFF
SW20.2
OFF
OFF
SW21.1
OFF
OFF
SW21.2
ON
ON
SW22.1
OFF
ON
SW22.2
ON
OFF
SW20.1
ON
SW20.2
OFF
SW21.1
ON
SW21.2
OFF
SW22.1
OFF
SW22.2
OFF
19
17
15
13
11
9
7
5
3
1
8
10
12
14
16
18
20
2
4
6
P10
ERM8_10X2_SMT
EDGE_M
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J3
ERF8_10X2_SMT
EDGE_F
3
5
6
7
8
4
2
1
SOIC8
U11
SN65LVDS2D
4
2
1
U10
SOT23-5
SN74LVC1G08
DNP
1
2
4
U9
SOT23-5
SN74LVC1G08
1
3
4
5
13
12
8
9
14
10
7
6
2
11
U8
SOIC16
ADM3202ARNZ
7
17
3-15-2010_15:12
SPDIF, RS-232, JTAG INTERFACES
2
1
CON012
J7
1
J6
CON012
2
1
JP2
IDC2X1
3
4
5
1
6
2
7
8
9
J2
CON038
R185
4.7K
0402
1
2
JP4
IDC2X1
C125
0402
0.01UF
0.01UF
0402
C121
C120
0.1UF
0402
0402
0.1UF
C119
0402
0.1UF
C118
C117
0.1UF
0402
R232
0603
15.0K
C127
0805
0.22UF
0603
10.0K
R231
0402
22
R230
R229
75.0
0603
C126
0805
0.22UF
C124
0402
0.01UF
DNP
R228
107.0
0805
0805
0.1UF
C123
R227
249.0
0805
0.01UF
0402
C122
0402
10K
R190
R99
10K
0402
1
3
5
7
9
11
13
2
4
6
8
10
12
14
P1
IDC7X2_SMTA
2
1
JP3
IDC2X1
8
1
2
7
3
6
5
4
16
15
14
13
12
11
10
9
SW19
DIP8
SWT016
1
2
4
3
SW21
DIP2
SWT020
1
2
4
3
SW20
DIP2
SWT020
1
2
4
3
SW22
DIP2
SWT020
Содержание ADSP-21479 EZ-Board
Страница 4: ......
Страница 10: ...Contents x ADSP 21479 EZ Board Evaluation System Manual ...
Страница 78: ...Connectors 2 30 ADSP 21479 EZ Board Evaluation System Manual ...
Страница 90: ...A 12 ADSP 21479 EZ Board Evaluation System Manual ...