Analog Devices ADSP-21479 EZ-Board, Руководство пользователя

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ADSP-21479 EZ-Board Evaluation System Manual 1-19
Using The ADSP-21479 EZ-Board
The shift register’s signals can be configured as follows.
• The
SR_SCLK
can come from any of the
SPORT0–7 SCLK
outputs,
PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin
(
SR_SCLK
).
• The
SR_LAT
can come from any of
SPORT0–7
frame sync outputs,
PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated
pin (
SR_LAT
).
• The
SR_SDI
input can from any of
SPORT0–7
serial data outputs,
any of the DAI pins (1–8), and one dedicated pin (
SR_SDI
).
Note that the
SR_SCLK
,
SR_LAT
, and
SR_SDI
inputs must come from the
same source, except in case of where
SR_SCLK
comes from PCGA/B or
SR_SCLK
and
SR_LAT
come from PCGA/B.
If
SR_SCLK
comes from PCGA/B, then
SPORT0–7
generate
SR_LAT
and
SR_SDI
signals. If
SR_SCLK
and
SR_LAT
come from PCGA/B, then
SPORT0–7
generate
SR_SDI
signal.
Access to the shift register of the processor is available via the shift register
interface connector (
P4
). Users can use a standard 2 mm ribbon cable if
they require off-board capabilities. For more information, see “Shift Reg-
ister Interface Connector (P4)” on page 2-27 .