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ADSP-2126x SHARC Processor Hardware Reference
10-15
Serial Peripheral Interface Port
When enabled as a master, the DMA engine transmits or receives data as
follows:
1. If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the SPI DMA FIFO. Data from the
DMA FIFO is loaded into the
TXSPI
register and then into the
Transmit Shift register. This initiates the transfer on the SPI port.
2. If configured to receive, data from
RXSPI
is automatically loaded
into the SPI DMA FIFO, the DMA engine reads data from the SPI
DMA FIFO and writes to memory. Finally, the SPI initiates the
receive transfer.
3. The SPI generates the programmed signal pulses on
SPICLK
and
simultaneously shifts data out of
MOSI
and shifts data in from
MISO
.
4. The SPI continues sending or receiving words until the SPI DMA
word count register transitions from 1 to 0.
If the DMA engine is unable to keep up with the transmit stream during a
transmit operation because the IOP requires the IOD (I/O data) bus to
service another DMA channel (or for another reason), the
SPICLK
stalls
until data is written into the
TXSPI
register. All aspects of SPI receive oper-
ation should be ignored. The data in the
RXSPI
register is not intended to
be used, and the
RXS
(bits 28–27 and 31–30 in the
SPCTLx
register) and
SPISTAT
bits (bits 26 and 29) should be ignored. The
ROVF
overrun condi-
tion cannot generate an error interrupt in this mode.
If the DMA engine cannot keep up with the receive data stream during
receive operations, then
SPICLK
stalls until data is read from
RXSPI
. While
performing a receive DMA, the processor core assumes the transmit buffer
is empty. If
SENDZ
= 1, the device repeatedly transmits 0’s on the
MOSI
pin.
Содержание ADSP-21261 SHARC
Страница 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Страница 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Страница 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Страница 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Страница 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...