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ADP1071-1EVALZ

 User Guide 

UG-1384 

 

Rev. 0 | Page 5 of 13 

EVALUATING THE ADP1071-1EVALZ BOARD 

Test points on the evaluation board allow the user to monitor 
output signals. The following sections provide descriptions of 
the typical results when evaluating the device in a multiflyback 
topology. The user can modify the operation of the device 
according to the 

ADP1071-1

/

ADP1071-2

 data sheet as needed.  

STARTUP  

When the supply voltage is on, the output voltages ramp up 
smoothly. For details about two-stage soft start, refer to the 

ADP1071-1

/

ADP1071-2

 data sheet. Figure 4 shows the startup 

under a no load condition, and Figure 5 shows the startup of a 
full load condition. 

CH1

  10.0V

CH2 10.0V

M40.0ms

A  CH1      9.60V

T

       9.0000ms

B

W

B

W

CH3

  10.0V

B

W

1

17050-

004

+24V

+5.5V

–15V

 

Figure 4. Startup at No Load 

CH1

  10.0V

CH2 10.0V

M40.0ms

A  CH1      9.60V

T

       9.0000ms

B

W

B

W

CH3

  10.0V

B

W

1

17050-

005

+24V

+5.5V

–15V

 

Figure 5. Startup at Full Load 

To experiment with different soft start timings, see more details 
in the soft start section in the 

ADP1071-1

/

ADP1071-2

 data 

sheet.  

CROSS REGULATION 

On the secondary side, the output voltage information of the 
5.5 V rail and the 24 V rail are sensed by a voltage divider 
network and sent to the FB pin. These two voltages (5.5 V and 
24 V) are partially regulated by a weightage ratio of 6:4. The 
−15 V rail is left quasi regulated due to its relatively low load 
current rating. The user can adjust the feedback weightage ratio 

according to the regulation requirement and load rating to 
achieve the most optimal cross regulation among the three 
outputs. Figure 6 through Figure 9 show the cross regulation 
performance under different load conditions.  

CH1

  500mA

CH2 1.00V

A  CH1      270mA

1

4

3

CH3

  5.00V

CH4 5.00V

5.5V LOAD STEP

0mA TO 500mA

+24V
AT FULL
LOAD

+5.5V

–15V

AT FULL

LOAD

17050-

006

 

Figure 6. Cross Regulation with Load Step at a +5.5 V Rail When +24 V and 

−15 V Rails at Full Load 

CH1

  500mA

CH2 1.00V

A  CH1      135mA

1

4

3

CH3

  5.00V

CH4 5.00V

5.5V LOAD STEP

0mA TO 500mA

+24V

+5.5V
AT FULL
LOAD

–15V

AT FULL

LOAD

17050-

007

 

Figure 7. Cross Regulation with Load Step at a +24 V Rail When +5.5 V and 

−15 V Rails at Full Load 

CH1

  500mA

CH2 1.00V

A  CH1      270mA

1

4

3

CH3

  5.00V

CH4 5.00V

5.5V LOAD STEP

0mA TO 500mA

+5.5V

+24V
AT NO
LOAD

–15V

AT NO

LOAD

17050-

008

 

Figure 8. Cross Regulation with Load Step at a +5.5 V Rail When +24 V and 

−15 V Rails at No Load 

Содержание ADP1071-1EVALZ

Страница 1: ...PMENT NEEDED DC power supply capable of 18 VDC to 32 VDC 1 A output current capability of the supply Electronic load capable of 15 W 0 V to 30 V rating capability of the load Oscilloscope capable of 5...

Страница 2: ...Train Overview 3 Transformer 3 Connectors 3 Caution 3 Evaluation Board Hardware 4 Evaluation Board Configurations 4 Powering Up 4 ADP1071 1EVALZ Dimensions 4 Evaluating the ADP1071 1EVALZ Board 5 Star...

Страница 3: ...l and C7 and C67 at the 15 V rail The snubber for the main switch is composed of D11 and D12 The ADP1071 1 flyback controller U1 is the power controller The power controller integrates gate drive for...

Страница 4: ...ads at the output terminals 2 Connect voltmeters on the input terminals VIN and VIN and output terminals 24 V 5 5 V 15 V and GND separately 3 Connect the voltage probes at different test pins Use the...

Страница 5: ...econdary side the output voltage information of the 5 5 V rail and the 24 V rail are sensed by a voltage divider network and sent to the FB pin These two voltages 5 5 V and 24 V are partially regulate...

Страница 6: ...ge of the main switch is clamped by the transient voltage suppressor TVS diode on the evaluation board The peak drain to source voltage occurs at the maximum input voltage The drain to source voltages...

Страница 7: ...ANCE Figure 15 shows the typical thermal image of the evaluation board at different operating conditions 17050 015 Figure 15 Thermal Image of the ADP1071 1 at 48 VDC Input Full Load No Airflow and 0 5...

Страница 8: ...56 46 4k R49 33k R35 33k C67 220uF P N C38 2 2 F D5 BZT52C11 7 F A C S1B D11 A C C7 10 F R24 0 976k C32 2200pF C4532X7R3D222K130KA C40 10nF C65 10 F R23 0 976k U1 ADP1071 1 GATE 1 AGND1 2 VREG1 3 MODE...

Страница 9: ...ADP1071 1EVALZ User Guide UG 1384 Rev 0 Page 9 of 13 17050 017 Figure 17 Board Outline 17050 018 Figure 18 Silkscreen Top 17050 019 Figure 19 Silkscreen Bottom 17050 020 Figure 20 PCB Layout Top Layer...

Страница 10: ...UG 1384 ADP1071 1EVALZ User Guide Rev 0 Page 10 of 13 17050 021 Figure 21 PCB Layout Layer 2 17050 022 Figure 22 PCB Layout Layer 3 17050 023 Figure 23 PCB Layout Layer 4...

Страница 11: ...AC 3 D11 Fairchild S1B 1 ESD suppressor TVS diode 400 W 43 V unidirect DO214AC_C D12 Vishay P4SMA43A E3 5A 2 Schottky diodes and rectifiers REC SOD123 2 A 200 V D16 D18 On Semiconductor MBR2H200SFT1G...

Страница 12: ...5 1206 R53 R54 Panasonic ERJ 8GEYJ103V 1 SMD resistor 10 k 0 25 W 5 1206 R55 Panasonic ERJ 8GEYJ103V 1 SMD resistor 46 4 k 1 8 W 1 0603 R56 4 SMD resistors 4 7 1 5 W 0 1 0603 R57 R58 R59 R60 1 Transf...

Страница 13: ...n Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemb...

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