UG-1098
ADE9000 Technical Reference Manual
Rev. 0 | Page 6 of 86
CRYSTAL OSCILLATOR/EXTERNAL CLOCK
The
contains a crystal oscillator. Alternatively, a
digital clock signal can be applied at the CLKIN pin of the
When a crystal is used as the clock source for the
attach the crystal and the ceramic capacitors, with capacitances
of CL1 and CL2, as shown in Figure 8. It is not recommended to
attach an external feedback resistor in parallel to the crystal.
When a digital clock signal is applied at the CLKIN pin, the
inverted output is available at the CLKOUT pin. This output is
not buffered internally and cannot be used to drive any other
external devices directly. Note that CLKOUT is available in
PSM0 operating mode only.
C
P1
C
L1
CLKIN
CLKOUT
29
30
C
P2
C
L2
1.75kΩ
2.5kΩ
C
IN1
C
IN2
24.576MHz
2.5MΩ
15523-
008
Figure 8. Crystal Application Circuit
Crystal Selection
The transconductance of the crystal oscillator circuit in the
, gm, is provided in the data sheet. It is recommended
to have 3 to 5 times more gm than the calculated gm
CRITICAL
for
the crystal.
The following equation shows how to calculate the gm
CRITICAL
for the crystal from information given in the crystal data sheet:
gm
CRITICAL
= 4 ×
ESR
MAX
× 1000 × (2 ×
π
×
f
CLK(Hz)
)
2
× (
C
0
+
C
L
)
2
where:
gm
CRITICAL
is the minimum gain required to start the crystal,
expressed in mA/V.
ESR
MAX
is the maximum ESR, expressed in ohms.
f
CLK
is 24.576 MHz, expressed in Hz as 24.576 × 10
6
.
C
0
is the maximum shunt capacitance, expressed in farads.
C
L
is the load capacitance, expressed in farads.
Crystals with low ESR and smaller load capacitance have a
lower gm
CRITICAL
and are easier to drive.
The
evaluation board uses a crystal manufactured by
Abracon (Part Number ABLS-24.576MHZ-8-L4Q-F-T), which
has a maximum ESR of 40 Ω, load capacitance of 8 pF, and
maximum shunt capacitance of 7 pF, which results in a gm
CRITICAL
of 0.86 mA/V:
gm
CRITICAL
= 4 ×
ESR
MAX
× 1000 × (2 ×
π
×
f
CLK(Hz)
)
2
× (
C
0
+
C
L
)
2
gm
CRITICAL
= 4 × 40 × 1000 × (2 ×
π
× 24.576 × 10
6
)
2
× (7 ×
10
−12
+ 8 × 10
−12
)
2
= 0.86
The gain of the crystal oscillator circuit in the
, gm,
provided in the data sheet is more than 5 times gm
CRITICAL
;
therefore, there is sufficient margin to start up this crystal.
Load Capacitor Calculation
Crystal manufacturers specify the combined load capacitance
across the crystal, CL. The capacitances in Figure 8 can be
described as follows:
•
CP
1
and CP
2
: parasitic capacitances on the clock pins
formed due to printed circuit board (PCB) traces.
•
Cin
1
and Cin
2
: internal capacitances of the CLKIN and
CLKOUT pins respectively.
•
CL
1
and CL
2
: selected load capacitors to get the correct
combined CL for the crystal.
The internal pin capacitances, C
in1
and C
in2
, are 4 pF each, as
shown in the data sheet. To find the values of CP
1
and CP
2
,
measure the capacitance on each of the clock pins of the PCB,
CLKIN and CLKOUT, respectively, with respect to the AGND
pin. If the measurement is done after soldering the IC to the
PCB, subtract out the 4 pF internal capacitance of the clock pins
to find the actual value of parasitic capacitance on each of the
crystal pins.
To select the appropriate capacitance value for the ceramic
capacitors, calculate CL
1
and CL
2
from the following equation:
CL
= [(
CL
1
+
CP
1
+
C
IN1
) × (
CL
2
+
CP
2
+
C
IN2
)]/(
CL
1
+
CP
1
+
C
IN1
+
CL
2
+
CP
2
+
C
IN2
)
(1)
Select CL
1
and CL
2
such that the total capacitance on each clock
pins is
CL
1
+
CP
1
+
C
IN1
=
CL
2
+
CP
2
+
C
IN2
(2)
Using Equation 1 and Equation 2, the values of CL
1
and CL
2
can
be calculated.
Load Capacitor Calculation Example
If a crystal with load capacitance specification of 8 pF is selected
and the measured parasitic capacitances from the PCB traces
are CP1 = CP2 = 2 pF, Equation 1 implies that
CL
= [(
CL
1
+
CP
1
+
C
IN1
) × (
CL
2
+
CP
2
+
C
IN2
)]/(
CL
1
+
CP
1
+
C
IN1
+
CL
2
+
CP
2
+
C
IN2
)
8 pF = [(
CL
1
+ 2 pF + 4 pF) × (
CL
2
+ 2 pF + 4 pF)]/(
CL
1
+
2 pF + 4 pF +
CL
2
+ 2 pF + 4 pF)
Assuming that CL
1
= CL
2
, to satisfy Equation 2,
8 pF = [(
CL
1
+ 6 pF) × (
CL
1
+ 6 pF)]/(
CL
1
+ 6 pF +
CL
1
+ 6 pF)
8 pF = [(
CL
1
+ 6 pF) × (
CL
1
+ 6 pF)]/[2 × (
CL
1
+ 6 pF)]
8 pF = (
CL
1
+ 6 pF)/2
Therefore, CL
1
= CL
2
= 10 pF.
Based on this example, 10 pF ceramic capacitors are selected for
CL
1
and CL
2
.
