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AD9843A

–6–

REV. 0

PIN CONFIGURATION

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AUX1IN

AVSS

AUX2IN

AVDD2

BYP4

NC

CCDIN

(LSB) D0

D1

D2

D3

D4

NC = NO CONNECT

D5

D6

D7

D8

BYP2

BYP1

AVDD1

AVSS

AD9843A

(MSB) D9

AVSS

SCK

SDATA

SL

NC

STBY

NC

THREE-STATE

DVSS

DVDD2

VRB

VRT

CML

DRVDD

DRVSS

DVSS

DATACLK

DVDD1

DVSS

PBLK

CLPOB

SHP

SHD

CLPDM

DVSS

DRVSS

DRVSS

PIN FUNCTION DESCRIPTIONS

Pin Number

Name

Type

Description

1, 2

DRVSS

P

Digital Driver Ground

3–12

D0–D9

DO

Digital Data Outputs

13

DRVDD

P

Digital Output Driver Supply

14

DRVSS

P

Digital Output Driver Ground

15, 18, 24, 41

DVSS

P

Digital Ground

16

DATACLK

DI

Digital Data Output Latch Clock

17

DVDD1

P

Digital Supply

19

PBLK

DI

Preblanking Clock Input

20

CLPOB

DI

Black Level Clamp Clock Input

21

SHP

DI

CDS Sampling Clock for CCD’s Reference Level

22

SHD

DI

CDS Sampling Clock for CCD’s Data Level

23

CLPDM

DI

Input Clamp Clock Input

25, 26, 35

AVSS

P

Analog Ground

27

AVDD1

P

Analog Supply

28

BYP1

AO

Internal Bias Level. Decoupling

29

BYP2

AO

Internal Bias Level Decoupling

30

CCDIN

AI

Analog Input for CCD Signal

31

NC

NC

Leave Floating or Decouple to Ground with 0.1 

F

32

BYP4

AO

Internal Bias Level Decoupling

33

AVDD2

P

Analog Supply

34

AUX2IN

AI

Analog Input

36

AUX1IN

AI

Analog Input

37

CML

AO

Internal Bias Level Decoupling

38

VRT

AO

A/D Converter Top Reference Voltage Decoupling

39

VRB

AO

A/D Converter Bottom Reference Voltage Decoupling

40

DVDD2

P

Digital Supply

42

THREE-STATE

DI

Digital Output Disable. Active High

43

NC

NC

May be tied High or Low. Should not be left floating.

44

STBY

DI

Standby Mode, Active High. Same as Serial Interface Standby Mode

45

NC

NC

Internally Not Connected. May be Tied High or Low

46

SL

DI

Serial Digital Interface Load Pulse

47

SDATA

DI

Serial Digital Interface Data

48

SCK

DI

Serial Digital Interface Clock

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

Содержание AD9843A

Страница 1: ...with 6 Bit Resolution 2 dB to 36 dB 10 Bit Variable Gain Amplifier VGA Low Noise Clamp Circuits Analog Preblanking Function 10 Bit 20 MSPS A D Converter Auxiliary Inputs with VGA and Input Clamp 3 Wir...

Страница 2: ...cale Input Voltage 2 0 V Data Output Coding Straight Binary VOLTAGE REFERENCE Reference Top Voltage VRT 2 0 V Reference Bottom Voltage VRB 1 0 V Specifications subject to change without notice DIGITAL...

Страница 3: ...2 dB See Page 13 for Gain Equations Max Gain VGA Code 1023 36 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output Min Clamp Level 0 LSB Max Clamp Level 63 75 LSB...

Страница 4: ...ODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Same as AUX1 MODE VGA Max Output Range 2 0 V p p Gain Control Resolution 512 Steps Gain Sel...

Страница 5: ...UTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD98...

Страница 6: ...s Reference Level 22 SHD DI CDS Sampling Clock for CCD s Data Level 23 CLPDM DI Input Clamp Clock Input 25 26 35 AVSS P Analog Ground 27 AVDD1 P Analog Supply 28 BYP1 AO Internal Bias Level Decoupling...

Страница 7: ...calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting The output noise can be converted to an equivalent voltage using the relationship 1 LSB AD...

Страница 8: ...60 80 90 15 VDD 3 3V VDD 3 0V VDD 2 7V TPC 1 Power vs Sample Rate 0 1000 400 200 600 800 0 0 5 0 5 0 25 0 25 TPC 2 Typical DNL Performance Typical Performance Characteristics VGA GAIN CODE LSB 4 2 0 0...

Страница 9: ...IVE PIXELS CLPOB CLPDM OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS PBLK NOTES 1 CLPOB AND CLPDM WILL OVERWRITE PBLK PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM...

Страница 10: ...OCCURS ON SL RISING EDGE Figure 8 Serial Write Operation SDATA SCK SL RNW TEST 1 0 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDS tDH tLS tLH NOTES 1 RNW READ NOT WRITE SET HIGH FOR READ OPERATION 2 TES...

Страница 11: ...nts Default Value x080 MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level LSB X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 25 0 0 0 0 0 0 1 0 0 5 1 1 1 1 1 1 1 0 63 5 1 1 1 1 1 1 1 1 63 75 Table V Con...

Страница 12: ...ee Tables V and VI for more details A CDS gain of 4 dB provides some front end signal gain and improves the overall signal to noise ratio This gain setting works very well in most applications and the...

Страница 13: ...Interface Timing and Inter nal Register Description section When the loop is disabled the Clamp Level Register may still be used to provide pro grammable offset adjustment Horizontal timing is shown i...

Страница 14: ...NAL V 0 8V 0 4V MIDSCALE 0dB TO 36dB Figure 14 AUX1 Circuit Configuration 0dB TO 18dB 8 AUX2IN BUFFER 0 1 F VIDEO SIGNAL 9 CLAMP LEVEL LPF VGA GAIN REGISTER ADC VGA VIDEO CLAMP CIRCUIT CLAMP LEVEL REG...

Страница 15: ...ins 25 through 39 This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins All decoupling ca...

Страница 16: ...inches and mm 48 Lead LQFP ST 48 TOP VIEW PINS DOWN 1 12 13 25 24 36 37 48 0 019 0 5 BSC 0 276 7 00 BSC SQ 0 011 0 27 0 006 0 17 0 354 9 00 BSC SQ 0 063 1 60 MAX 0 030 0 75 0 018 0 45 0 008 0 2 0 004...

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