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–3–

REV. 0

AD9843A

Parameter

Min

Typ

Max

Unit

Notes

P

OWER CONSUMPTION

78

mW

See TPC 1 for Power Curves

MAXIMUM CLOCK RATE

20

MHz

CDS

Allowable CCD Reset Transient

1

500

mV

See Input Waveform in Note 1

Max CCD Black Pixel Amplitude

1

200

mV

Max Input Range Before Saturation

1

1.0

V p-p

With 4 dB CDS Gain

Max Input Range Before Saturation

1.5

V p-p

With –2 dB CDS Gain

Max Input Range Before Saturation

0.5

V p-p

With 10 dB CDS Gain

Max Output Range

1.6

V p-p

At Any CDS Gain Setting

Gain Resolution

64

Steps

Gain Range (Two’s Complement Coding)

See Figure 12 for CDS Gain Curve

Min Gain (CDS Gain Register Code 32)

–2

dB

Medium Gain (CDS Gain Code 63)

4

dB

4 dB Is Default with CDS Gain Disabled

Max Gain (CDS Gain Code 31)

10

dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range

1.6

V p-p

Max Output Range

2.0

V p-p

Gain Control Resolution

1024

Steps

Gain Monotonicity

             Guaranteed

Gain Range

See Figure 13 for VGA

 

Gain Curve

Low Gain (VGA Register Code 91)

2

dB

See Page 13 for Gain Equations

Max Gain (VGA Code 1023)

36

dB

BLACK LEVEL CLAMP

Clamp Level Resolution

256

Steps

Clamp Level

Measured at ADC Output

Min Clamp Level

0

LSB

Max Clamp Level

63.75

LSB

SYSTEM PERFORMANCE

Specifications Include Entire Signal Chain

Gain Accuracy, VGA Code 91 to 1023

–0.5

+0.5

dB

Use Equations on Page 13 to Calculate Gain

Peak Nonlinearity, 500 mV Input Signal

0.1

%

12 dB Gain Applied (4 dB CDS Gain)

Peak Nonlinearity, 800 mV Input Signal

0.4

%

8 dB Gain Applied (4 dB CDS Gain)

Total Output Noise

0.2

LSB rms

AC Grounded Input, 6 dB Gain Applied

Power Supply Rejection (PSR)

40

dB

Measured with Step Change on Supply

POWER-UP RECOVERY TIME

Clocks Must Be Applied, as in Figures 5 and 6

From Fast Recovery Mode

0.1

ms

From Reference Standby Mode

1

ms

From Total Shutdown Mode

3

ms

From Power-Off Condition

15

ms

NOTES

1

Input Signal Characteristics defined as follows, with 4 dB CDS gain:

1V MAX

INPUT

SIGNAL RANGE

200mV MAX

OPTICAL

BLACK PIXEL

500mV TYP

RESET

TRANSIENT

Specifications subject to change without notice.

CCD-MODE SPECIFICATIONS

(T

MIN

 to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

 = f

SHP

 = f

SHD

 = 20 MHz, unless otherwise noted.)

Содержание AD9843A

Страница 1: ...with 6 Bit Resolution 2 dB to 36 dB 10 Bit Variable Gain Amplifier VGA Low Noise Clamp Circuits Analog Preblanking Function 10 Bit 20 MSPS A D Converter Auxiliary Inputs with VGA and Input Clamp 3 Wir...

Страница 2: ...cale Input Voltage 2 0 V Data Output Coding Straight Binary VOLTAGE REFERENCE Reference Top Voltage VRT 2 0 V Reference Bottom Voltage VRB 1 0 V Specifications subject to change without notice DIGITAL...

Страница 3: ...2 dB See Page 13 for Gain Equations Max Gain VGA Code 1023 36 dB BLACK LEVEL CLAMP Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output Min Clamp Level 0 LSB Max Clamp Level 63 75 LSB...

Страница 4: ...ODE SPECIFICATIONS Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Same as AUX1 MODE VGA Max Output Range 2 0 V p p Gain Control Resolution 512 Steps Gain Sel...

Страница 5: ...UTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD98...

Страница 6: ...s Reference Level 22 SHD DI CDS Sampling Clock for CCD s Data Level 23 CLPDM DI Input Clamp Clock Input 25 26 35 AVSS P Analog Ground 27 AVDD1 P Analog Supply 28 BYP1 AO Internal Bias Level Decoupling...

Страница 7: ...calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting The output noise can be converted to an equivalent voltage using the relationship 1 LSB AD...

Страница 8: ...60 80 90 15 VDD 3 3V VDD 3 0V VDD 2 7V TPC 1 Power vs Sample Rate 0 1000 400 200 600 800 0 0 5 0 5 0 25 0 25 TPC 2 Typical DNL Performance Typical Performance Characteristics VGA GAIN CODE LSB 4 2 0 0...

Страница 9: ...IVE PIXELS CLPOB CLPDM OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS PBLK NOTES 1 CLPOB AND CLPDM WILL OVERWRITE PBLK PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM...

Страница 10: ...OCCURS ON SL RISING EDGE Figure 8 Serial Write Operation SDATA SCK SL RNW TEST 1 0 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 tDS tDH tLS tLH NOTES 1 RNW READ NOT WRITE SET HIGH FOR READ OPERATION 2 TES...

Страница 11: ...nts Default Value x080 MSB LSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Clamp Level LSB X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 25 0 0 0 0 0 0 1 0 0 5 1 1 1 1 1 1 1 0 63 5 1 1 1 1 1 1 1 1 63 75 Table V Con...

Страница 12: ...ee Tables V and VI for more details A CDS gain of 4 dB provides some front end signal gain and improves the overall signal to noise ratio This gain setting works very well in most applications and the...

Страница 13: ...Interface Timing and Inter nal Register Description section When the loop is disabled the Clamp Level Register may still be used to provide pro grammable offset adjustment Horizontal timing is shown i...

Страница 14: ...NAL V 0 8V 0 4V MIDSCALE 0dB TO 36dB Figure 14 AUX1 Circuit Configuration 0dB TO 18dB 8 AUX2IN BUFFER 0 1 F VIDEO SIGNAL 9 CLAMP LEVEL LPF VGA GAIN REGISTER ADC VGA VIDEO CLAMP CIRCUIT CLAMP LEVEL REG...

Страница 15: ...ins 25 through 39 This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins All decoupling ca...

Страница 16: ...inches and mm 48 Lead LQFP ST 48 TOP VIEW PINS DOWN 1 12 13 25 24 36 37 48 0 019 0 5 BSC 0 276 7 00 BSC SQ 0 011 0 27 0 006 0 17 0 354 9 00 BSC SQ 0 063 1 60 MAX 0 030 0 75 0 018 0 45 0 008 0 2 0 004...

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