AD9695 External Trigger Quick Start Guide
7.
Apply the rising edge on J5. This edge needs to be applied before the end of the Fill Delay interval specified in Step 4. If
10000 was entered in Step 6, you will have 10000 milliseconds from when the Run button was pushed, to apply the
edge.
8.
After the Fill Delay interval has passed, data that was captured by external trigger will appear graphically on the Visual
Analog canvas. Note that the data will not appear when the trigger edge is applied, but actually after the Fill Delay has
passed. Save the data as desired.
Figure 8: Successful Data Capture
TROUBLESHOOTING
1. The data capture is not waiting for an external input / is acting like a normal capture / is triggering
instantly/constantly.
The external pin must be driven for external trigger mode – if it is left floating, the FPGA will function as though it is not i n
external trigger mode, regardless of the mode it is put into. Check your input and make sure that it is not floating and that
the timing of the signal is setup correctly.
2. The data capture is timing out before a capture is taken / I’m getting the following error message:
Figure 9: FIFO Timeout
The FPGA did not see a rising edge or the FPGA polling time may not be set for a long enough time – see Step 4. If the
polling time is not long enough to see the input trigger, or the input trigger is not timed to coincide with the capture time,
the data capture may time out. Ensure that the polling time is set in milliseconds, and not seconds. The voltage or
frequency of the input pulse may need to be adjusted, if the polling time is correct. Additionally, this could be a normal
error with the evaluation board such as with the JESD lane timing and the input/reference clocks , etc. Make sure that you
are getting a regular capture without the external trigger mode.
