AD9695 External Trigger Quick Start Guide
4.
Clicking the Settings button above will bring up a window with three tabs. In the Capture Board tab, enter a number
like 10000 into the Fill Delay (ms) field. This is the amount of time the FPGA will poll the FIFO for a data capture before
timing out. Program the FPGA with the appropriate .bin file if not already programmed.
Figure 5: Capture Board Tab
5.
In the Device tab, click the Enable External Trigger checkbox (as well as any other settings necessary to your setup,
such as Enable Alternate REFCLK). This will program the FPGA for External Trigger Mode.
Figure 6: Device Tab
6.
Now the evaluation setup is configured for externally triggered capture. Push the Run button on the VisualAnalog top
bar.
Figure 7: Data Capture Run Button
The evaluation board will now wait for a rising edge to be applied to J5. The rising edge on J5 should wait for a ready status
from the FPGA – if it is sent before, the FPGA may not capture data.
