Analog Devices AD9516 Скачать руководство пользователя страница 6

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UG-075

Evaluation Board User Guide

Rev. 0 | Page 6 of 16

Program the R (reference) divider by clicking the

R DIVIDER

box at the top of the main window. Set

the desired value and click

(see Figure 12

)

Program the N (feedback) divider by clicking the

N DIVIDER

box at top of the main window. Set the

desired value and click

. For the example, N = 200

can use 8/9 dual modulus mode with A = 0 and B = 25.

Set the charge pump current by clicking the

CHARGE

PUMP

box in the upper right corner of the main window,

and then click

Note that if the desired configuration has the phase
detector frequency above 50 MHz, an antibacklash pulse
width of 1.3 ns may work better. This setting is accessed by
clicking the

PFD

button to the left of the

CHARGE PUMP

box. However, this setting normally does not need to be
modified.

10.

Set the VCO divider by clicking the green

VCO

box in the

center of the main window, immediately to the left of the

Cal VCO

button.

11.

Power down unused drivers, click the numbered triangular
symbol on the right side of the main window (see Figure 7),
select

2 - Safe Power Down

, and click

(see Figure 20

)

745

-024

Figure 7. Driver Symbol

12.

Set the channel dividers by clicking

DIVIDER 0

through

DIVIDER 4

and enter the divider ratio.

13.

Click the flashing red

WRITE

button under the

REGISTER W/R

section. This loads the desired settings

to the AD951x evaluation board,

14.

Click the blinking yellow

Cal VCO

button to load the

VCO calibration window. The default VCO divide ratio
(16) works for all applications. Click the

Cal VCO

button

in the

Calibrate VCO

window to begin calibration (see

Figure 17). The PLL should now be locked and the

(lock detect) LED on the left side of the board should be on.

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Содержание AD9516

Страница 1: ...16 x AD9517 x and AD9518 x are very low noise PLL clock synthesizers featuring an integrated VCO clock dividers and up to 14 outputs The AD9516 features automatic holdover and a flexible reference inp...

Страница 2: ...tware Components 7 Main Window 7 PLL Reference Input Window 8 PLL Configuration Window 8 REFMON STATUS and LD Buttons 8 Register W R Box 9 SYNC PD Power Down and RESET Buttons 9 Reference R Divider Wi...

Страница 3: ...damaged SIGNAL CONNECTIONS To connect signals use the following steps 1 Connect a signal generator to the J10 SMA connector By default the reference inputs on this evaluation board are ac coupled and...

Страница 4: ...ware Depending on whether the evaluation board was found by the software either light blue text appears in a pop up window indicating that the evaluation board was found or red text appears indicating...

Страница 5: ...ox found at the top of the main window see Figure 8 2 Enter the intended reference input frequency in megahertz in the REF 1 MHz box at the upper left corner of the main window 3 Click the triangular...

Страница 6: ...is setting normally does not need to be modified 10 Set the VCO divider by clicking the green VCO box in the center of the main window immediately to the left of the Cal VCO button 11 Power down unuse...

Страница 7: ...listed in the following sections and each of these has its own window From the main window each functional block can be accessed by clicking that block in the main window When a subwindow closes after...

Страница 8: ...The SyncB Counter Reset Mode section indicates whether the R A and B counters are reset when the SYNC pin is activated and controls R0x019 7 6 See the AD951x data sheet for more details The ReadBack...

Страница 9: ...e R DIVIDER box on the main window It allows you to set the reference divider If this box is colored gray the PLL is off To turn the PLL on click the PLL MODE box at the top of the main window and sel...

Страница 10: ...tter with the 1 3 ns antibacklash pulse width setting Setting the lock detect counter to values greater then 5 PFD cycles can be useful in applications where the loop bandwidth is low and the lock det...

Страница 11: ...g However to have the new phase take effect the SYNC signal needs to be toggled by using the SYNC button in the lower left corner of the main window 08745 015 Figure 18 Divider 1 Settings Window LVPEC...

Страница 12: ...f delay is shown in the right half of the window The feature is described in detail in the AD951x data sheet 08745 017 08745 018 Figure 22 Output 6 Delay Window DEBUG WINDOW The Debug window shown in...

Страница 13: ...w allows you to select which evaluation board the software is controlling Click Refresh List to detect a recently connected evaluation board see Figure 25 08745 020 Figure 25 Select USB Device Window...

Страница 14: ...Ethernet line cards as well as applications where the reference clock is relatively high jitter the low loop BW loop filter shown in Table 3 is a better choice It has a flat transfer function with pe...

Страница 15: ...reference clock is noisy or for cases where the frequency planning requires a phase detector frequency of 1 MHz or lower Table 3 AD9516 Evaluation Board Low Loop Bandwidth Clock Cleanup Filter Compon...

Страница 16: ...of evaluation boards Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of pa...

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