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Evaluation Board User Guide

UG-075

One

 

Technology

 

Way

 

 

P.O.

 

Box

 

9106

 

 

Norwood,

 

MA

 

02062-9106,

 

U.S.A.

 

 

Tel:

 

781.329.4700

 

 

Fax:

 

781.461.3113

 

 

www.analog.com 

 

AD9516-x, AD9517-x, and AD9518-x Evaluation Board 

 

See the last page for an important warning and disclaimers.

 

Rev. 0 | Page 1 of 16 

FEATURES 

Simple power connection using 6 V wall adapter and  

on-board LDO voltage regulators 

LDOs are easily bypassed for power measurements 
8 ac-coupled differential LVPECL SMA connectors 
2 ac-coupled LVPECL differential headers 
2 dc-coupled differential LVDS SMA connectors that are 

reconfigurable to four CMOS SMA connectors 

2 dc-coupled LVDS differential headers that are 

reconfigurable to four CMOS connectors 

SMA connectors for  

2 reference inputs 
Charge pump output 
Clock distribution input 

USB connection to PC 
Microsoft Windows-based evaluation software with simple 

graphical user interface 

On-board PLL loop filter 
Easy access to digital I/O and diagnostic signals  

via I/O header 

Status LEDs for diagnostic signals 

APPLICATIONS 

Clocking of analog-to-digital and digital-to-analog 

converters up to 2.9 GHz 

Networking and communications line cards 
Test and measurement equipment 
Wireless base stations, controllers 
Clock cleanup/jitter attenuation 
Clock distribution 

GENERAL DESCRIPTION 

The AD9516-x, AD9517-x, and AD9518-x are very low noise 
PLL clock synthesizers featuring an integrated VCO, clock 
dividers, and up to 14 outputs. The AD9516 features automatic 
holdover and a flexible reference input circuit allowing for very 
smooth reference clock switching. The AD9516 family also 
features the necessary provisions for an external VCXO.  

The AD9516 evaluation board is a compact, easy-to-use 
platform for evaluating all features of the AD9516. This user 
guide covers all six versions of the AD9516 family, as well as  
the AD9517 and AD9518 families (hereafter referred to as 
AD951x). The AD9516, AD9517, and AD9518 differ only  
in package size, and the number of outputs. The evaluation 
software main window for the AD9517 and AD9518 reflects 
fewer outputs, but the operation is identical for all devices. 

Although the Quick Start Guide to the AD9516 PLL section 
applies specifically to the AD9516-3, increasing the N (feed-
back) divider and channel divider increases the VCO frequency 
to the allowable frequency range of other AD9516 versions. 

For the AD9516-5, which lacks an internal VCO, certain 
portions of this document that apply to the internal VCO  
(such as VCO calibration) can be ignored. 

For convenience, detailed information from the AD9516 data 
sheet has been included here. Use this user guide in conjunction 
with the AD9516, AD9517, and AD9518 data sheets, as well as 
additional documentation available at 

www.analog.com

AD9516 EVALUATION BOARD 

0874

5-

001

 

Figure 1. 

www.BDTIC.com/ADI

Содержание AD9516

Страница 1: ...16 x AD9517 x and AD9518 x are very low noise PLL clock synthesizers featuring an integrated VCO clock dividers and up to 14 outputs The AD9516 features automatic holdover and a flexible reference inp...

Страница 2: ...tware Components 7 Main Window 7 PLL Reference Input Window 8 PLL Configuration Window 8 REFMON STATUS and LD Buttons 8 Register W R Box 9 SYNC PD Power Down and RESET Buttons 9 Reference R Divider Wi...

Страница 3: ...damaged SIGNAL CONNECTIONS To connect signals use the following steps 1 Connect a signal generator to the J10 SMA connector By default the reference inputs on this evaluation board are ac coupled and...

Страница 4: ...ware Depending on whether the evaluation board was found by the software either light blue text appears in a pop up window indicating that the evaluation board was found or red text appears indicating...

Страница 5: ...ox found at the top of the main window see Figure 8 2 Enter the intended reference input frequency in megahertz in the REF 1 MHz box at the upper left corner of the main window 3 Click the triangular...

Страница 6: ...is setting normally does not need to be modified 10 Set the VCO divider by clicking the green VCO box in the center of the main window immediately to the left of the Cal VCO button 11 Power down unuse...

Страница 7: ...listed in the following sections and each of these has its own window From the main window each functional block can be accessed by clicking that block in the main window When a subwindow closes after...

Страница 8: ...The SyncB Counter Reset Mode section indicates whether the R A and B counters are reset when the SYNC pin is activated and controls R0x019 7 6 See the AD951x data sheet for more details The ReadBack...

Страница 9: ...e R DIVIDER box on the main window It allows you to set the reference divider If this box is colored gray the PLL is off To turn the PLL on click the PLL MODE box at the top of the main window and sel...

Страница 10: ...tter with the 1 3 ns antibacklash pulse width setting Setting the lock detect counter to values greater then 5 PFD cycles can be useful in applications where the loop bandwidth is low and the lock det...

Страница 11: ...g However to have the new phase take effect the SYNC signal needs to be toggled by using the SYNC button in the lower left corner of the main window 08745 015 Figure 18 Divider 1 Settings Window LVPEC...

Страница 12: ...f delay is shown in the right half of the window The feature is described in detail in the AD951x data sheet 08745 017 08745 018 Figure 22 Output 6 Delay Window DEBUG WINDOW The Debug window shown in...

Страница 13: ...w allows you to select which evaluation board the software is controlling Click Refresh List to detect a recently connected evaluation board see Figure 25 08745 020 Figure 25 Select USB Device Window...

Страница 14: ...Ethernet line cards as well as applications where the reference clock is relatively high jitter the low loop BW loop filter shown in Table 3 is a better choice It has a flat transfer function with pe...

Страница 15: ...reference clock is noisy or for cases where the frequency planning requires a phase detector frequency of 1 MHz or lower Table 3 AD9516 Evaluation Board Low Loop Bandwidth Clock Cleanup Filter Compon...

Страница 16: ...of evaluation boards Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of pa...

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