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Evaluation Board User Guide 

UG-075

 

Rev. 0 | Page 5 of 16 

QUICK START GUIDE TO THE AD9516 PLL 

When the evaluation software is installed, the evaluation board 
is connected, and the software is loaded, use the following steps 
to configure and lock the PLL. These steps assume that the input 
signal is present, the evaluation board has not been modified, 
and that the PLL loop filter is suitable for the user’s application. 

This quick start guide covers only simple PLL operation to  
start the PLL. See the AD9516 data sheet and Evaluation 
Software Components s
ection for a detailed explanation  
of the various AD9516 features.  

The following case is an example for the AD9516-3 using the 
values in Table 1. 

Table 1.  

Parameter Value 

Input Frequency 

20 MHz on REF1 

Output Frequency 

200 MHz on OUT1 

Reference Divider 

Phase Detector Frequency 

10 MHz 

Feedback Divider 

200 

VCO Frequency 

2000 MHz 

VCO Divider 

Channel Divider 

1.

 

Turn the PLL on by selecting 

Normal Op 

from the 

PLL 

MODE

 box found at the top of the main window (see 

Figure 8). 

2.

 

Enter the intended reference input frequency (in 
megahertz) in the 

REF 1 (MHz)

 box at the upper left 

corner of the main window. 

3.

 

Click the triangular buffer symbol immediately to the right 
of the input reference frequency (see Figure 4) boxes to load 
the 

Reference Input Control

 window shown in Figure 5

Turn the REF1 reference input buffer on by selecting the 

Enable REF1

 check box, and then clicking 

OK

.  

0

8

745

-00

6

 

Figure 4. Buffer Symbol 

 

0

874

5-

00

4

 

Figure 5. Reference Input Control Window 

4.

 

When the window closes, the 

WRITE

 button under the 

REGISTER W/R

 section in the main window blinks red. 

This indicates there are settings that have not been loaded 
to the AD9516 evaluation board. Click the blinking red 

WRITE

 button to load these settings to the evaluation 

board. 

5.

 

Select the VCO as the input to the clock distribution 
circuitry by clicking the mux symbol that is located 
immediately to the right of the 

VCO (MHz)

 box (see 

Figure 6). 

08

745

-0

23

 

Figure 6. Buffer Symbol 

When the VCO is selected, the border of the 

VCO (MHz)

 

box changes from gray to black. The current VCO 
frequency is shown in the 

VCO (MHz)

 box.  

 

www.BDTIC.com/ADI

Содержание AD9516

Страница 1: ...16 x AD9517 x and AD9518 x are very low noise PLL clock synthesizers featuring an integrated VCO clock dividers and up to 14 outputs The AD9516 features automatic holdover and a flexible reference inp...

Страница 2: ...tware Components 7 Main Window 7 PLL Reference Input Window 8 PLL Configuration Window 8 REFMON STATUS and LD Buttons 8 Register W R Box 9 SYNC PD Power Down and RESET Buttons 9 Reference R Divider Wi...

Страница 3: ...damaged SIGNAL CONNECTIONS To connect signals use the following steps 1 Connect a signal generator to the J10 SMA connector By default the reference inputs on this evaluation board are ac coupled and...

Страница 4: ...ware Depending on whether the evaluation board was found by the software either light blue text appears in a pop up window indicating that the evaluation board was found or red text appears indicating...

Страница 5: ...ox found at the top of the main window see Figure 8 2 Enter the intended reference input frequency in megahertz in the REF 1 MHz box at the upper left corner of the main window 3 Click the triangular...

Страница 6: ...is setting normally does not need to be modified 10 Set the VCO divider by clicking the green VCO box in the center of the main window immediately to the left of the Cal VCO button 11 Power down unuse...

Страница 7: ...listed in the following sections and each of these has its own window From the main window each functional block can be accessed by clicking that block in the main window When a subwindow closes after...

Страница 8: ...The SyncB Counter Reset Mode section indicates whether the R A and B counters are reset when the SYNC pin is activated and controls R0x019 7 6 See the AD951x data sheet for more details The ReadBack...

Страница 9: ...e R DIVIDER box on the main window It allows you to set the reference divider If this box is colored gray the PLL is off To turn the PLL on click the PLL MODE box at the top of the main window and sel...

Страница 10: ...tter with the 1 3 ns antibacklash pulse width setting Setting the lock detect counter to values greater then 5 PFD cycles can be useful in applications where the loop bandwidth is low and the lock det...

Страница 11: ...g However to have the new phase take effect the SYNC signal needs to be toggled by using the SYNC button in the lower left corner of the main window 08745 015 Figure 18 Divider 1 Settings Window LVPEC...

Страница 12: ...f delay is shown in the right half of the window The feature is described in detail in the AD951x data sheet 08745 017 08745 018 Figure 22 Output 6 Delay Window DEBUG WINDOW The Debug window shown in...

Страница 13: ...w allows you to select which evaluation board the software is controlling Click Refresh List to detect a recently connected evaluation board see Figure 25 08745 020 Figure 25 Select USB Device Window...

Страница 14: ...Ethernet line cards as well as applications where the reference clock is relatively high jitter the low loop BW loop filter shown in Table 3 is a better choice It has a flat transfer function with pe...

Страница 15: ...reference clock is noisy or for cases where the frequency planning requires a phase detector frequency of 1 MHz or lower Table 3 AD9516 Evaluation Board Low Loop Bandwidth Clock Cleanup Filter Compon...

Страница 16: ...of evaluation boards Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of pa...

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