AD9510/PCB
Rev. 0 | Page 18 of 28
Clock Inputs Section
Figure 23 shows the clock inputs section of the main interface window. It contains the settings for the three clock inputs: REFCLK, CLK1,
and CLK2. These list boxes let you input the clock frequencies so that the PLL and output frequencies can be calculated automatically.
The maximum input frequencies are 1500 MHz for CLK1 and CLK2, and 250 MHz for REFCLK. If the entered values exceed these
amounts, the list box is outlined in red. If you try to continue, an error message is not given; however, all calculations based on the
entered value are invalid.
CLOCK INPUT
POWER DOWN
CLOCK INPUT TO
PLL DRIVER
CLOCK INPUT
SELECT MUX
FREQUENCY
INPUT BOXES
05632-023
Figure 23. Clock Inputs, Main Interface Window
Additionally, left-clicking on any of the driver-signal graphics brings up the window shown in Figure 24. This clock input settings window
allows for power down of each of the clock inputs as well as clock select for the distribution section. The clock select for the distribution
section can also be changed by left-clicking on the mux symbol in the clock inputs section.
CLOCK INPUT SELECT
CLOCK INPUT AND
PLL DRIVER
POWER-DOWN
05632-024
Figure 24. Clock Input Settings Window
