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AD5934

 

Rev. A | Page 13 of 40 

TRANSMIT STAGE 

As shown in Figure 16, the transmit stage of the AD5934 is made 
up of a 27-bit phase accumulator DDS core that provides the output 
excitation signal at a particular frequency. The input to the phase 
accumulator is taken from the contents of the start frequency register 
(see Register Address 0x82, Register Address 0x83, and Register 
Address 0x84). Although the phase accumulator offers 27 bits of 
resolution, the start frequency register has the three most significant 
bits (MSBs) set to 0 internally; therefore, the user has the ability to 
program only the lower 24 bits of the start frequency register. 

 PHASE

ACCUMULATOR

(27 BITS)

VOUT

R

OUT

DAC

R(GAIN)

V

BIAS

0

532

5-

03

4

 

Figure 16. Transmit Stage 

The AD5934 offers a frequency resolution programmable by the 
user down to 0.1 Hz. The frequency resolution is programmed via 
a 24-bit word loaded serially over the I

2

C interface to the frequency 

increment register. 

The frequency sweep is fully described by the programming of 
three parameters: the start frequency, the frequency increment, 
and the number of increments. 

Start Frequency 

This is a 24-bit word that is programmed to the on-board RAM  
at Register Address 0x82, Register Address 0x83, and Register 
Address 0x84 (see the Register Map section). The required code 
loaded to the start frequency register is the result of the formula 
shown in Equation 1, based on the master clock frequency and the 
required start frequency output from the DDS. 

27

2

16

×

⎟⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎝

⎛

=

MCLK

Frequency

Start

Output

Required

Code

Frequency

Start

 (1) 

For example, if the user requires the sweep to begin at 30 kHz and 
has a 16 MHz clock signal connected to MCLK, the code that needs 
to be programmed is given by 

0x3D70A3

2

16

MHz

16

kHz

30

27

=

×

⎟⎟

⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

=

Code

Frequency

Start

 

The user programs the value of 0x3D to Register Address 0x82, 
the value 0x70 to Register Address 0x83, and the value 0xA3 to 
Register Address 0x84. 

 

 

 

 

Frequency Increment 

This is a 24-bit word that is programmed to the on-board RAM at 
Register Address 0x85, Register Address 0x86, and Register Address 
0x87 (see the Register Map section). The required code loaded to 
the frequency increment register is the result of the formula shown in 
Equation 2, based on the master clock frequency and the required 
increment frequency output from the DDS. 

27

2

16

×

⎟⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎝

⎛

=

MCLK

Increment

Frequency

Required

Code

Increment

Frequency

 (2) 

For example, if the user requires the sweep to have a resolution of 
10 Hz and has a 16 MHz clock signal connected to MCLK, the code 
that needs to be programmed is given by 

0x00053E

16

MHz

16

Hz

10

≡

⎟⎟

⎟

⎟

⎟

⎠

⎞

⎜⎜

⎜

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

=

Code

Increment

Frequency

 

The user programs the value 0x00 to Register Address 0x85, the 
value 0x05 to Register Address 0x86, and the value 0x3E to 
Register Address 0x87. 

Number of Increments 

This is a 9-bit word that represents the number of frequency 
points in the sweep. The number is programmed to the on-board 
RAM at Register Address 0x88 and Register Address 0x89 (see the 
Register Map section). The maximum number of points that can 
be programmed is 511. 

For example, if the sweep needs 150 points, the user programs  
the value 0x00 to Register Address 0x88 and the value 0x96 to 
Register Address 0x89. 

Once the three parameter values are programmed, the sweep is 
initiated by issuing a start frequency sweep command to the 
control register at Register Address 0x80 and Register Address 
0x81 (see the Register Map section). Bit D2 in the status register 
(Register Address 0x8F) indicates the completion of the frequency 
measurement for each sweep point. Incrementing to the next 
frequency sweep point is under the control of the user. The measured 
result is stored in the two register groups that follow: 0x94, 0x95 
(real data) and 0x96, 0x97 (imaginary data) that should be read 
before issuing an increment frequency command to the control 
register to move to the next sweep point. There is the facility to 
repeat the current frequency point measurement by issuing a 
repeat frequency command to the control register. This has the 
benefit of allowing the user to average successive readings. When 
the frequency sweep has completed all frequency points, Bit D3 in 
the status register is set, indicating the completion of the sweep. 
Once this bit is set, further increments are disabled.  

 

Содержание AD5934

Страница 1: ...dance spectroscopy Complex impedance measurement Corrosion monitoring and protection equipment Biomedical and automotive sensors Proximity sensing Nondestructive testing Material property analysis Fuel battery cell condition monitoring GENERAL DESCRIPTION The AD5934 is a high precision impedance converter system solution that combines an on board frequency generator with a 12 bit 250 kSPS analog t...

Страница 2: ... 0x81 22 Start Frequency Register Register Address 0x82 Register Address 0x83 Register Address 0x84 23 Frequency Increment Register Register Address 0x85 Register Address 0x86 Register Address 0x87 23 Number of Increments Register Register Address 0x88 Register Address 0x89 24 Number of Settling Time Cycles Register Register Address 0x8A Register Address 0x8B 24 Status Register Register Address 0x...

Страница 3: ...tion Using Gain Factor Section 15 Changes to Figure 20 16 Changes to Impedance Error Section 17 Added Measuring the Phase Across an Impedance Section 19 Added Figure 28 and Figure 29 Renumbered Sequentially 20 Added Table 6 Renumbered Sequentially 20 Deleted Table 8 19 Deleted Table 10 and Table 11 20 Changes to Table 9 22 Deleted Table 14 Table 16 and Table 17 22 Changes to Status Register Regist...

Страница 4: ...ange 1 AC Output Excitation Voltage3 1 98 V p p Refer to Figure 4 for output voltage distribution DC Bias4 1 48 V DC bias of the ac excitation signal see Figure 5 DC Output Impedance 200 Ω TA 25 C Short Circuit Current to Ground atVOUT 5 8 mA TA 25 C Range 2 AC Output Excitation Voltage3 0 97 V p p See Figure 6 DC Bias4 0 76 V DC bias of output excitation signal see Figure 7 DC Output Impedance 2 ...

Страница 5: ...ol Register section 9 mA VDD 5 5 V IDD Power Down Mode 0 7 5 μA VDD 3 3 V 1 8 μA VDD 5 5 V 1 Temperature range for Y version 40 C to 125 C typical at 25 C 2 The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934 3 The peak to peak value of the ac output excitation voltage scales with supply voltage according to the following formula VDD is the...

Страница 6: ...0 300 ns max tR rise time of SDA when transmitting 0 ns min tR rise time of SCL and SDA when receiving CMOS compatible t11 300 ns max tF fall time of SCL and SDA when transmitting 0 ns min tF fall time of SDA when receiving CMOS compatible 250 ns max tF fall time of SDA when receiving 20 0 1 Cb 3 ns min tF fall time of SCL and SDA when transmitting Cb 400 pF max Capacitive load for each bus line 1...

Страница 7: ...erature Range 65 C to 160 C Maximum Junction Temperature 150 C SSOP Package Thermal Impedance θJA 139 C W θJC 136 C W Reflow Soldering Pb Free Peak Temperature 260 C Time at Peak Temperature 10 sec to 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other condit...

Страница 8: ...re 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 to 3 7 NC No Connect 4 RFB External Feedback Resistor Connect from Pin 4 to Pin 5 This pin sets the gain of the current to voltage amplifier on the receive side 5 VIN Input to Receive Transimpedance Amplifier VIN presents a virtual earth voltage of VDD 2 6 VOUT Excitation Voltage Signal Output 8 MCLK The master ...

Страница 9: ...OLTAGE V 0 95 0 96 0 97 0 98 0 99 1 00 1 01 1 02 MEAN 0 9862 SIGMA 0 0041 Figure 6 Range 2 Output Excitation Voltage Distribution VDD 3 3 V 0 68 0 86 05325 073 VOLTAGE V 0 70 0 72 0 74 0 76 0 78 0 80 0 82 0 84 MEAN 0 7543 SIGMA 0 0099 30 0 NUMBER OF DEVICES 25 20 15 10 5 Figure 7 Range 2 DC Bias Distribution VDD 3 3 V 30 0 0 370 0 400 05325 077 VOLTAGE V NUMBER OF DEVICES 25 20 15 10 5 0 375 0 380...

Страница 10: ...MA 0 0024 30 0 NUMBER OF DEVICES 25 20 15 10 5 Figure 11 Range 4 DC Bias Distribution VDD 3 3 V 15 8 10 8 0 18 05325 088 MCLK FREQUENCY MHz IDD mA 15 3 14 8 14 3 13 8 13 3 12 8 12 3 11 8 11 3 AVDD1 AVDD2 DVDD CONNECTED TOGETHER OUTPUT EXCITATION FREQUENCY 30kHz RFB ZCALIBRATION 100kΩ 2 4 6 8 10 12 14 16 Figure 12 Typical Supply Current IDD vs MCLK Frequency 0 4 1 0 0 400 05325 028 PHASE Degrees PH...

Страница 11: ...largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 Hz to Nyquist bandwidth The narrow band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 200 kHz about the fundamental frequency Signal to Noise Ratio SNR SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquis...

Страница 12: ... Figure 15 Impedance vs Frequency Profile The AD5934 permits the user to perform a frequency sweep with a user defined start frequency frequency resolution and number of points in the sweep In addition the device allows the user to program the peak to peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the VOUT and VIN pins Table 5 gives ...

Страница 13: ...ister Address 0x86 and Register Address 0x87 see the Register Map section The required code loaded to the frequency increment register is the result of the formula shown in Equation 2 based on the master clock frequency and the required increment frequency output from the DDS 27 2 16 MCLK Increment Frequency Required Code Increment Frequency 2 For example if the user requires the sweep to have a r...

Страница 14: ... in the control register see the Control Register section and is made available at the VOUT pin RECEIVE STAGE The receive stage comprises a current to voltage amplifier followed by a programmable gain amplifier PGA antialiasing filter and ADC The receive stage schematic is shown in Figure 17 The unknown impedance is connected between the VOUT and VIN pins The first stage current to voltage amplifi...

Страница 15: ...y point conversion would then be Real Data Register 0xF064 3996 decimal Imaginary Data Register 0x227E 8830 decimal 106 9692 8830 3996 2 2 Magnitude Magnitude Impedance 1 Code Admittance Factor Gain 12 10 819 515 106 9692 kΩ 200 1 Factor Gain IMPEDANCE CALCULATION USING GAIN FACTOR The next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedanc...

Страница 16: ... 1 035682 10 9 1 031224 10 9 4 458000 10 12 Frequency span of sweep ΔF is 10 kHz Therefore the gain factor required at 60 kHz is given by 9 10 1 031224 kHz 5 kHz 10 12 4 458000E The required gain factor is 1 033453 10 9 The impedance is calculated as previously described in the Impedance Calculation section GAIN FACTOR SETUP CONFIGURATION When calculating the gain factor it is important that the r...

Страница 17: ...OUT was calibrated out in the gain factor calculations In Figure 22 to Figure 26 the 10 kHz excitation frequency was generated using a 4 MHz clock Impedance Range 1 0 1 kΩ to 1 kΩ The following conditions were used to conduct the tests shown in Figure 22 Output excitation voltage 2 V p p Calibration impedance value ZCALIBRATION 100 Ω PGA gain 1 Supply voltage 3 3 V Current to voltage amplifier gai...

Страница 18: ... 2 0 2 5 3 0 500kΩ 1MΩ RFB 100kΩ CALIBRATION IMPEDANCE 100kΩ TA 25 C Figure 25 Impedance Range 4 Typical Impedance Error over Frequency Impedance Range 5 1 MΩ to 2 MΩ The following conditions were used to conduct the tests shown in Figure 26 Output excitation voltage 2 V p p Calibration impedance value ZCALIBRATION 100 kΩ PGA gain 1 Supply voltage 3 3 V Current to voltage amplifier gain resistor 1...

Страница 19: ...d between the VOUT and VIN pins of the AD5934 The parameters of interest for many users are the magnitude of the impedance ZUNKNOWN and the impedance phase ZØ The measurement of the impedance phase ZØ is a 2 step process The first step involves calculating the AD5934 system phase The AD5934 system phase can be calculated by placing a resistor across the VOUT and VIN pins of the AD5934 and calculat...

Страница 20: ...sary to add an additional 180 to calculate the correct standard angle Likewise when the real and imaginary components are both negative that is when data lies in the third quadrant the arctangent formula returns a positive angle and it is necessary to add an additional 180 to calculate the correct standard phase When the real component is positive and the imaginary component is negative that is th...

Страница 21: ... PROGRAM INITIALIZE WITH START FREQUENCY COMMAND TO THE CONTROL REGISTER AFTER A SUFFICIENT AMOUNT OF SETTLING TIME HAS ELAPSED PROGRAM START FREQUENCY SWEEP COMMAND IN THE CONTROL REGISTER POLL STATUS REGISTER TO CHECK IF THE DFT CONVERSION IS COMPLETE RESET BY ISSUING A RESET COMMAND TO THE CONTROL REGISTER THE DEVICE IS PLACED IN STANDBY MODE PROGRAM THE INCREMENT FREQUENCY OR THE REPEAT FREQUE...

Страница 22: ...ter Address 0x80 and to not alter the contents of Register Address 0x81 Note that the control register should not be written to as part of a block write command The control register also allows the user to program the excitation voltage and set the system clock A reset command to the control register does not reset any programmed values associated with the sweep that is start frequency number of i...

Страница 23: ...nitialize with start frequency command is required to restart the frequency sweep command sequence Output Voltage Range The output voltage range allows the user to program the excitation voltage range at VOUT PGA Gain The PGA gain allows the user to amplify the response signal into the ADC by a multiplication factor of 5 or 1 START FREQUENCY REGISTER REGISTER ADDRESS 0x82 REGISTER ADDRESS 0x83 REG...

Страница 24: ...1 are don t care bits The maximum number of output cycles that can be programmed is 511 4 2044 cycles For example consider an excitation signal of 30 kHz the maximum delay between the programming of this frequency and the time that this signal is first sampled by the ADC is 511 4 33 33 μs 68 126 ms The ADC takes 1024 samples and the result is stored as real data and imaginary data in Register Addr...

Страница 25: ...INARY DATA REGISTERS 16 BITS REGISTER ADDRESS 0x94 REGISTER ADDRESS 0x95 REGISTER ADDRESS 0x96 REGISTER ADDRESS 0x97 These registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point The values are stored in 16 bit twos complement format To convert this number to an actual impedance value the magnitude Imaginary Real 2 2...

Страница 26: ... followed by an acknowledge bit which can be from the master or slave device Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low to high transition when the clock is high can be interpreted as a stop signal If the operation is a write operation the first data byte after the slave address is a command byte Thi...

Страница 27: ...ER DATA A W A A P 05325 049 Figure 32 Writing Register Data to Register Address In the AD5934 the write byte protocol is also used to set a pointer to a register address see Figure 33 This protocol is used for a subsequent single byte read from the same address block read or block write starting at that address To set a register pointer the following sequence is applied 1 The master device asserts...

Страница 28: ...gure 36 The start address for a block read must previously have been set by setting the address pointer 1 The master device asserts a start condition on SDA 2 The master sends the 7 bit slave address followed by the write bit low 3 The addressed slave device asserts an acknowledge on SDA 4 The master sends a command code 1010 0001 that tells the slave device to expect a block read 5 The slave asse...

Страница 29: ...olerance from device to device like all discrete resistors manufactured in a silicon fabrication process Typical values of the output series resistance are outlined in Table 16 Table 16 Output Series Resistance ROUT vs Excitation Range Parameter Value Typ Output Series Resistance Value Range 1 2 V p p 200 Ω typical Range 2 1 V p p 2 4 kΩ typical Range 3 0 4 V p p 1 0 kΩ typical Range 4 0 2 V p p 6...

Страница 30: ... pin increases the peak to peak signal presented to the ADC input from 400 mV RFB 100 Ω to 2 V p p RFB 500 Ω The gain factor calculated is for a 100 Ω resistor connected between VOUT and VIN assuming the output series resistance of the external amplifier is small enough to be ignored When biasing the circuit shown in Figure 37 note that the receive side of the AD5934 is hard biased about VDD 2 by ...

Страница 31: ...f a car is parked over the coil the impedance of the coil changes and the AD5934 detects the presence of the car ELECTRO IMPEDANCE SPECTROSCOPY The AD5934 has found use in the area of corrosion monitoring Corrosion in a metal such as aluminum which is used in air craft and ships requires continuous assessment because the metal is exposed to a wide variety of conditions such as temperature and mois...

Страница 32: ...an 100 μA of quiescent current It also provides good noise performance at 8 μV p p in the 0 1 Hz to 10 Hz range Long term drift is a measure of how much the reference drifts over time A reference with a tight long term drift specification ensures that the overall solution remains stable during its lifetime A reference with a tight temperature coefficient specification should be chosen to reduce th...

Страница 33: ...mportant that the 0 1 μF capacitor has low effective series resistance ESR and effective series inductance ESI common ceramic types of capacitors are suitable The 0 1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching The power supply line itself should have as large a trace as possible to provide a low impedance p...

Страница 34: ...dows XP A schematic of the evaluation board is shown in Figure 40 and Figure 41 USING THE AD5934 EVALUATION BOARD The evaluation board is a test system designed to simplify the evaluation of the AD5934 The evaluation board data sheet that is available with the evaluation board gives full information on how to operate the evaluation board Further evaluation information is available from www analog ...

Страница 35: ...AD5934 Rev A Page 35 of 40 SCHEMATICS 05325 144 Figure 40 EVAL AD5934EBZ USB Schematic ...

Страница 36: ...AD5934 Rev A Page 36 of 40 05325 145 Figure 41 EVAL AD5934EBZ Schematic ...

Страница 37: ...AD5934 Rev A Page 37 of 40 05325 146 Figure 42 Linear Regulator on EVAL AD5934EBZ ...

Страница 38: ...AD5934 Rev A Page 38 of 40 05325 147 Figure 43 Decoupling on the EVAL AD5934EBZ ...

Страница 39: ... wrap pins 200 kΩ R1 8WA2 FEC 93415011 R33 No 4 kΩ through hole resistor Not inserted4 R43 No 20 kΩ through hole resistor Not inserted4 R5 R6 Yes SMD resistors 100 kΩ 0603 FEC 93304021 R7 Yes SMD resistor 0 Ω 0603 FEC 93316621 R8 R9 Yes SMD resistors 2 2 kΩ 0603 FEC 93308101 R10 Yes SMD resistor 10 kΩ 0603 FEC 93303991 R11 Yes SMD resistor 1 kΩ 0805 FEC 93323831 R12 R13 Yes SMD resistors 20 kΩ 060...

Страница 40: ... Lead Shrink Small Outline Package SSOP RS 16 AD5934YRSZ REEL71 40 C to 125 C 16 Lead Shrink Small Outline Package SSOP RS 16 EVAL AD5934EBZ1 40 C to 125 C Evaluation Board T 1 Z RoHS Compliant Part Purchase of licensed I2 C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2 C Patent Rights to use these components in...

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