Analog Devices AD5934, Руководство пользователя, Страница: 22 / 40

AD5934
Rev. A | Page 22 of 40
REGISTER MAP
Table 7.
Register Name Register Address Bits Function
Control 0x80 D15 to D8 Read/write
0x81 D7 to D0 Read/write
Start Frequency 0x82 D23 to D16 Read/write
0x83 D15 to D8 Read/write
0x84 D7 to D0 Read/write
Frequency Increment 0x85 D23 to D16 Read/write
0x86 D15 to D8 Read/write
0x87 D7 to D0 Read/write
Number of Increments 0x88 D15 to D8 Read/write
0x89 D7 to D0 Read/write
Number of Settling Time Cycles 0x8A D15 to D8 Read/write
0x8B D7 to D0 Read/write
Status 0x8F D7 to D0 Read only
Real Data 0x94 D15 to D8 Read only
0x95 D7 to D0 Read only
Imaginary Data 0x96 D15 to D8 Read only
0x97 D7 to D0 Read only
CONTROL REGISTER (REGISTER ADDRESS 0x80,
REGISTER ADDRESS 0x81)
The AD5934 contains a 16-bit control register (Register Address
0x80 and Register Address 0x81) that sets the control modes.
The default value of the control register upon reset is as follows:
D15 to D0 is reset to 0xA000 upon power-up.
The four MSBs of the control register are decoded to provide
control functions, such as performing a frequency sweep,
powering down the part, and controlling various other functions
defined in the control register map.
The user can choose to write only to Register Address 0x80 and
to not alter the contents of Register Address 0x81. Note that the
control register should not be written to as part of a block write
command. The control register also allows the user to program
the excitation voltage and set the system clock. A reset command
to the control register does not reset any programmed values
associated with the sweep (that is, start frequency, number of
increments, frequency increment). After a reset command,
an initialize with start frequency command must be issued to
the control register to restart the frequency sweep sequence
(see Figure 30).
Table 8. D10 to D9 Control Register Map
D10 D9 Range No. Output Voltage Range
0 0 1 2.0 V p-p typical
0 1 3 200 mV p-p typical
1 0 4 400 mV p-p typical
1 1 2 1.0 V p-p typical
Table 9. D11 and D8 to D0 Control Register Map
Bits Description
D11 No operation
D8 PGA gain; 0 = ×5, 1 = ×1
D7 Reserved; set to 0
D6 Reserved; set to 0
D5 Reserved; set to 0
D4 Reset
D3 External system clock; set to 1
Internal system clock; set to 0
D2 Reserved; set to 0
D1 Reserved; set to 0
D0 Reserved; set to 0
Table 10. D15 to D12 Control Register Map
D15 D14 D13 D12 Description
0 0 0 0 No operation
0 0 0 1 Initialize with start frequency
0 0 1 0 Start frequency sweep
0 0 1 1 Increment frequency
0 1 0 0 Repeat frequency
1 0 0 0 No operation
1 0 0 1 No operation
1 0 1 0 Power-down mode
1 0 1 1 Standby mode
1 1 0 0 No operation
1 1 0 1 No operation