Ampro LittleBoard 800, Справочное руководство

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Chapter 3 Hardware
LittleBoard 800 Reference Manual 51
Table 3-20. Ethernet Port 1 Pin/Signal Descriptions (J23)
Pin # Signal Description
1 TX+
2 TX-
Analog Twisted Pair Ethernet Transmit Differential Pair – These pins transmit the
serial bit stream for transmission on the Unshielded Twisted Pair Cable (UTP).
These signals interface directly with an isolation transformer.
3 RX+
6 RX-
Analog Twisted Pair Ethernet Receive Differential Pair – These pins receive the
serial bit stream from the isolation transformer.
4, 5,
7, 8 CT_TP Center Tap – Connected to center tap of transformer and floating ground while
isolated from board common ground by 1000pf capacitor.
9 SPEED Speed LED – Indicates which transfer rate is being used, 10BaseT or 100BaseT.
10 VCC3 +3.3 Volts – Voltage for plus side of LEDs.
11 LINK Link LED – Indicates a Link is established between this port and another device.
12 ACT Activity LED – Indicates Activity is occurring on the Ethernet link.
13, 14 SHLD Shields – Connected to common board ground.
Note: The shaded area denotes power or ground.
Gigabit Ethernet Controller (U11)
The Intel® 82541(in GI or PI versions) Gigabit Ethernet Controller is 32-bit wide, PCI 2.3 compliant
controller capable of transmitting and receiving data rates of 1000 Mbps, 100 Mbps, or 10 Mbps and
transferring data over the PCI interface at 33MHz. The 82541GI/PI’s gigabit MAC design fully
integrates the physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for
1000BaseT, 100BaseTX, and 10BaseT applications (802.3, 802.3u, and 802.3ab).
The 82541GI/PI controller delivers high performance, PCI bus efficiency, with wide internal data paths
to eliminate performance bottlenecks by efficiently handling large address and data words. This
controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that
maximizes the use of bursts for efficient bus usage. This controller caches up to 64 packet descriptors in
a single burst with a large 64kByte on-chip packet buffer to maintain superior performance with efficient
PCI bandwidth use, as available PCI bandwidth changes. In addition, using hardware acceleration, the
controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP
segmentation. The 82541GI/PI Gigabit Ethernet controller supports or provides the following features:
•
Low-latency transmit and receive queues to prevent waiting periods or buffer overflow
•
Supports caches of 64 packet descriptors in a signal burst to provide efficient PCI bandwidth use
•
Supports programmable host memory receive buffers (256 Bytes to 16kBytes) and cache line
sizes (16 to 256 Bytes)
•
Supports wide optimized internal data paths for low latency data handling and superior DMA
transfer rates
•
Supports 64kByte configurable Transmit and Receive FIFO buffers
•
Supports simple programming model with descriptor ring transmit and receive management
hardware
•
Supports jumbo frames of 16kByte transmit and receive packets
•
Supports maximized system performance and throughput with interrupt reduction of transmit and
receive operations
•
Full duplex or half-duplex support at 10Mbps, 100Mbps, and 1000Mbps
•
Supports 1000BaseT 4-wire pairs and 10/100BaseT 2-wire pairs
•
IEEE 802.3x 10BaseT/100BaseT/1000BaseT compatible physical layer to wire transformer