Chapter 2 WINBIOS Setup
45
Chipset Setup
Memory Hole
This option allows the end user to specify a
memory hole. The settings are
Disabled, 512-
640K,
or
15-16M
(from 15 MB to 16 MB). The
Optimal and Fail-Safe default settings are
Disabled.
DRAM Speed
This option specifies the RAS access time for the
DRAM used in the computer for system memory.
The settings are
60ns
or
70ns.
The Optimal and
Fail-Safe default settings are
70ns.
PCI Burst Mode
When set to
Enabled,
this option enables the PCI
Bursting bit in the Intel Triton chipset. Graphics
display problem can occur if certain devices, such
as the Cirrus 5434 chip, are installed and PCI
Burst mode is enabled. Most of the time, setting
this option to Enabled increases the PCI bus data
transfer rate. The settings are
Enabled
or
Disabled.
The Optimal default setting is
Enabled.
The Fail-
Safe default setting is
Disabled.
PCI Concurrency
Set this option to
Enabled
to permit the CPU to
remain active while activity occurs on the PCI bus.
The settings are
Enabled
or
Disabled.
The Optimal
default setting is
Enabled.
The Fail-Safe default
setting is
Disabled.
PCI Streaming
Set this option to
Enabled
to permit long data
transmissions (streaming operations) on the PCI
bus. The settings are
Enabled
or
Disabled.
The
Optimal default setting is
Enabled.
The Fail-Safe
default setting is
Disabled.