AMD Elan SC520, Руководство пользователя

Страница: 69 / 444

System Initialization
Élan™SC520 Microcontroller User’s Manual 3-13
3.7.3 PAR Register Priority
The PAR register mechanism is a very flexible and useful one. It is designed to allow the
system programmer to easily program the address decoding and set attributes for
addressable regions. One feature of the PAR register system that may not be obvious from
the examples included in this chapter is that the PAR registers have a priority mechanism.
The highest priority PAR register is PAR 0 and the lowest priority register is PAR 15. This
feature is not relevant unless two (or more) PAR regions overlap. If they do overlap, then
the higher priority PAR register takes precedence.
The PAR registers are used to modify and add to the default system addressing (see
Table 4-4 on page 4-4). Note that the system can function quite well with all of the PAR
registers disabled. For example, a system could start-up, use a PAR register to copy the
contents of Flash to SDRAM
1
, jump to the code in SDRAM, and then disable the PAR
register used for the copy. With all the PAR registers disabled, the normal address resolution
priorities in the system govern addressing of physical devices.
3.7.4 External GP Bus Devices
Devices on the GP bus can be addressed in two ways. Each is controlled by programming
the PAR registers.
■ By chip select, mapping the device into memory or I/O space
■
Devices can do their own memory or I/O address decoding.
Programming a PAR register with the GP bus as the target is required to cause memory
or I/O cycles to be forwarded to the external GP bus. This is true for devices that use chip
selects and devices that decode their own address (generate their own chip selects).
Programming a PAR register is necessary because, by default, memory and I/O cycles
generated by the Am5
x
86 CPU that are not decoded by an internal GP bus peripheral or
memory resources (like SDRAM, ROM, and the MMCR registers) go to the PCI bus.
For a device on the external GP bus, programming a PAR register configures the following
characteristics:
■ Target device field—For either a GP bus memory-mapped cycle or an I/O cycle
■
Attribute field—For the particular GP bus chip select to which the device is attached
■ Memory page size field— Most peripherals use a 4-Kbyte granularity. Peripherals that
have very large memory address spaces, such as SDRAM or ROM, might need to use
a 64-Kbyte granularity.
■
Region size and start address
For a device that requires a chip select from the ÉlanSC520 microcontroller, the chip select
must be mapped to a physical pin using the PIO registers. For devices that do their own
address decoding, the PAR register must still be programmed, and the chip select should
be chosen; however, the chip select from the PAR register does not need to be mapped to
a physical pin.
Note: All of the internal peripherals on the GP bus are decoded at fixed locations. The
locations for these peripherals cannot be changed by programming a PAR register. For
example, the internal real-time clock cannot be moved to a different location. No PAR
registers are required to access any of the internal peripheral devices on the ÉlanSC520
microcontroller.
1. This is one way to shadow a BIOS to DRAM.