AMD Elan SC520, Руководство пользователя

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SDRAM Controller
10-20 Élan™SC520 Microcontroller User’s Manual
10.5.5.4 Operation Mode Select
The ÉlanSC520 microcontroller provides an SDRAM Operation Mode Select
(OPMODE_SEL) bit field in the SDRAM Control (DRCCTL) register (MMCR offset 10h).
These bits are used to select a particular mode of operation of the SDRAM controller.
■
The default mode of operation is normal SDRAM mode. This is the mode in which the
SDRAM controller must be configured for data access.
■
The NOP, All Banks Precharge, Load Mode Register, and Auto Refresh commands
specified by the OPMODE_SEL bit field are primarily used for SDRAM device
initialization.
When specifying NOP, All Banks Precharge, Load Mode Register, or Auto Refresh
commands, the command is not actually applied to the SDRAM devices until an Am5
x
86
CPU access to SDRAM occurs (either a read or write cycle).
The write buffer must be disabled prior to utilizing the NOP, All Banks Precharge, Load
Mode Register, or Auto Refresh OPMODE_SEL bit field if the Am5
x
86 CPU cycle executed
to generate these cycle types to the SDRAM devices is a write cycle.
The All Banks Precharge command should be issued prior to bank configuration changes.
This places the SDRAM devices in an idle state and clears the SDRAM controller’s page
table entries.
See “SDRAM Device Initialization” on page 10-30 for more information.
10.5.6 SDRAM Timing Configuration
The ÉlanSC520 microcontroller provides independent timing configuration for SDRAM
devices. The following timing parameters are configurable:
■
CAS latency (C
L
)
■ RAS precharge (T
RP
)
■
RAS-to-CAS delay (T
RCD
)
■ RAS-to-RAS or auto-refresh-to-RAS (T
RC
)
Note that the write recovery time (T
WR
) parameter is fixed to 2T (where T refers to a 15-ns
clock period for a 33.333-MHz crystal).
10.5.6.1 CAS Latency (C
L
)
The CAS latency (C
L
) of an SDRAM device specifies the number of clocks between a read
command being issued until the first piece of read data is available. After this delay, read
data is returned on each subsequent clock.
The ÉlanSC520 microcontroller supports CAS latency options for either 2T or 3T (where
T refers to a 15-ns clock period for a 33.333-MHz crystal). This parameter is a configuration
option, since some SDRAM devices have slightly better access timing when configured for
C
L
= 3. The CAS_LAT bit in the SDRAM Timing Control (DRCTMCTL) register (MMCR
offset 12h) is used to specify this value.
The C
L
parameter is programmed into the device with the Load Mode Register command.
See “SDRAM Device Initialization” on page 10-30 for more information.