AMD Elan SC520, Руководство пользователя

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SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-17
To avoid this, whenever a single byte is to be written to the SDRAM (or for that matter, any
number of bytes that is less than the full doubleword), ECC first reads the whole data word,
checks for any single- or multi-bit errors, and, if any are present, generates the
corresponding interrupt and corrects the data (for a single-bit error), modifies the necessary
bytes, and then generates the check-bits across the modified four bytes. Finally, the entire
ECC word is stored back into memory. This process is called a
read-modify-write operation.
If a full doubleword is written, then there is no need for a read-modify-write cycle. Also, a
partial doubleword write to a write-protected region does not generate a read-modify-write
cycle.
Since seven check-bits are required for each bank of SDRAM if ECC is enabled, ECC
cannot be supported if 168-pin (72-bit) SDRAM DIMMS are used. If a single 168-pin (72-
bit) DIMM is used for supporting two banks, then ECC cannot be enabled due to lack of
extra check bits in the DIMM. In this case, extra SDRAM devices must be used to store the
check-bits.
To assist in the development of software to handle ECC single-bit and multi-bit errors, the
ECC Check Code Test (ECCCKTEST) register (MMCR offset 23h) is provided. This register
can be used to override the automatically-generated ECC check code with a user-provided
check code for the following SDRAM write access.
10.5.4 Buffering
The ÉlanSC520 microcontroller includes two buffering techniques to optimize the memory
system performance. These include the write buffer and read buffer.
When enabled, the write buffer effectively decouples master write activity from incurring
the SDRAM latency penalty. This, in effect, also leaves SDRAM free to satisfy a higher
demand in read activity by all masters. In addition, the write buffer provides write merge
and write collapse functions to better utilize FIFO storage and reduce the number of
transactions to SDRAM. The read merge function is also provided to reduce data coherency
overhead by eliminating the need to flush the write buffer prior to a read access. During a
read request, should the write buffer contain more recent data than SDRAM, the data from
the write buffer is merged with data returned from SDRAM, eliminating the need to flush
the write buffer.
The ÉlanSC520 microcontroller supports a Read-Around-Write feature when the write
buffer is enabled. When the write buffer is enabled, the SDRAM controller’s arbiter favors
read activity, effectively giving read priority to SDRAM over write data that has been posted
in the write buffer. This feature is intended to increase master read performance.
The read buffer provides two cache lines (32 bytes total) of storage for read data returned
from SDRAM. Read requests that can be retrieved from the read buffer can be provided in
zero wait states to the requesting master. The SDRAM controller always fetches an entire
cache line of data from the SDRAM and stores it in the read buffer, independently of the
amount of data requested during the master access. For example, during a read request
from a non-bursting master (i.e., single doubleword request), the SDRAM controller fetches
the entire cache line of data from SDRAM and stores it in the read buffer.
The read buffer’s read-ahead function, when enabled, provides a mechanism to prefetch
the cache line of information from SDRAM that immediately follows the requested cache
line. This is in anticipation of future accesses to the prefetched line. The read-ahead feature
of the read buffer enhances read burst activity by the Am5
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86 CPU and external PCI master
burst read requests. Read prefetches, when enabled, occur only for read burst transfer
requests of two or more doublewords. Single doubleword read requests do not cause a
read-ahead buffer prefetch of the next cache line; they only cause the cache line of the