PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual
9-19
9.5.4.2
PCI Bus Command Support
As a PCI bus target, the ÉlanSC520 microcontroller’s PCI host bridge treats the memory-
write-and-invalidate command the same as a memory-write cycle. When either of these
commands is issued by a PCI bus master, the PCI host bridge and system arbitration blocks
force the Am5
x
86 CPU’s integrated cache to snoop the addresses prior to writing the data
to SDRAM. If the cache detects a modified cache line at the same address, it writes back
and invalidates the line. If the CPU is operating in write-through cache mode, the line is
simply invalidated and the data is written to SDRAM.
The PCI host bridge does not respond to configuration cycles or special cycles issued by
external PCI bus masters. Interrupt acknowledge cycles and special cycles are not
forwarded to the PCI bus.
9.5.4.3
DEVSEL Timing
When an external PCI bus master accesses the ÉlanSC520 microcontroller’s SDRAM, the
PCI host bridge always asserts DEVSEL with medium timing (two clocks after FRAME is
asserted). The ÉlanSC520 microcontroller does not serve as a subtractive decode agent
on the PCI bus.
9.5.4.4
Delayed Transaction Support
External PCI bus master reads of the ÉlanSC520 microcontroller’s SDRAM can be
configured to be delayed transactions This maximizes PCI bus efficiency by freeing up the
bus while the initial SDRAM read request is issued to the SDRAM controller.
When the Automatic Delayed Transaction Enable (T_DLYTR_ENB) field is set in the Host
Bridge Control (HBCTL) register (MMCR offset 60h), the PCI host bridge immediately issues
a retry to the external PCI bus master read cycle and begins requesting the data from the
SDRAM controller. The external PCI bus master read cycle is retried until
any of the
requested data has been read into the target read FIFO. Only the first doubleword requested
needs to be read into the target read FIFO before the PCI host bridge completes the delayed
transaction instead of retrying it again. After the PCI host bridge responds to the delayed
transaction, it continues to prefetch data and provides all the data requested (up to 64
doublewords maximum) by the external PCI bus master without disconnecting.
When a delayed transaction read cycle is pending (waiting for the originating external PCI
bus master to retry the transaction), all other read transactions are terminated with a retry.
The PCI host bridge supports one outstanding delayed transaction, so these retried
transactions are not latched. Write transactions, however, are allowed to complete and are
placed in the PCI host bridge target write FIFO. A delayed transaction discard timer is
provided so that a broken master does not deadlock the system. If, after 2
15
PCI clocks, a
master has not retried a delayed transaction, the transaction is discarded and an interrupt
can be optionally generated. The delayed transaction discard timer is fixed at 2
15
PCI clocks.
When external PCI bus master reads of ÉlanSC520 microcontroller’s SDRAM are not
configured as automatic delayed transactions, the PCI host bridge tries to return the
requested data to the PCI bus master without issuing a retry. Wait states are inserted into
the transaction until the data is read from SDRAM. If the initial data cannot be returned in
32 clocks, the PCI host bridge terminates the transaction with a retry and latches the read
transaction as a delayed transaction to comply with the
PCI Local Bus Specification,
Revision 2.2. Note that if any data is pending in the Am5
x
86 CPU-to-PCI posted-write latch,
it must be flushed before read data can be returned to an external PCI master by the PCI
host bridge target controller. In this case, the PCI host bridge immediately retries the external
PCI master read transaction and latches the request as a delayed transaction.
Содержание Elan SC520
Страница 1: ...lan SC520 Microcontroller User s Manual Order 22004A...
Страница 4: ...iv lan SC520 Microcontroller User s Manual...
Страница 28: ...Introduction xxviii lan SC520 Microcontroller User s Manual...
Страница 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...
Страница 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
Страница 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...
Страница 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...
Страница 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...
Страница 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...
Страница 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...
Страница 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
Страница 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...
Страница 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
Страница 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...
Страница 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
Страница 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...