System Arbitration
8-8
Élan™SC520 Microcontroller User’s Manual
8.4.3.1
PCI Bus Arbitration Protocol
The
PCI Local Bus Specification, Revision 2.2, states that the central arbiter must implement
a fairness algorithm, which means that each potential bus master must be granted access
to the bus independently of other requests. The PCI bus arbiter satisfies this requirement
by implementing a rotating priority arbitration scheme that guarantees each bus master a
place in the arbitration rotation (see Figure 8-3 on page 8-6 for information on rotating
priority arbitration).
Rotating priority mode alone may not provide adequate arbitration in a system where it is
known that some PCI bus masters require more bandwidth than others. Therefore, the
ÉlanSC520 microcontroller’s PCI bus arbiter has two rotating priority queues to
accommodate this requirement: a high-priority queue and a low-priority queue.
The masters in the high-priority queue are granted more bandwidth than masters in the
low-priority queue. The high-priority queue can contain up to two PCI masters, and the low-
priority queue contains all masters that are not in the high-priority queue. The
HI_PRI_0_SEL and HI_PRI_1_SEL bit fields in the Arbiter Priority Control (ARBPRICTL)
register (MMCR offset 74h) are used to specify the position of each PCI master in the high-
priority queue.
Both queues have rotating priority, and one low-priority master is granted the bus for every
rotation of the high-priority queue. After the low-priority master is granted the bus, the low-
priority queue rotates to the next low-priority master (see Figure 8-4).
Any one or two (or none) of the ÉlanSC520 microcontroller’s PCI bus masters can be placed
in the high-priority queue. Note that programming the same bus master for both slots in the
high-priority queue
does provide additional performance for that master. The net result of
programming the same master in both slots of the high-priority queue is that the master is
given tenure during both slots. If no masters are in the high-priority queue, then there is
one rotating priority queue where each master has equal priority.
The high and low-priority queues are for external PCI bus masters, and the Am5
x
86 CPU
PCI master adds an additional level of arbitration. The PCI bus arbiter can be configured
with the CPU_PRI bit field in the Arbiter Priority Control (ARBPRICTL) register to grant the
bus to the Am5
x
86 CPU after every one, two, or three external PCI transactions (where the
external PCI master to be granted the bus is determined from the high and low-priority
queues). This implements another rotating priority queue (see Figure 8-5).
See the
PCI Local Bus Specification, Revision 2.2, for detailed requirements of PCI bus
arbitration.
Содержание Elan SC520
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Страница 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...
Страница 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
Страница 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...
Страница 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...
Страница 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...
Страница 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...
Страница 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...
Страница 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
Страница 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...
Страница 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
Страница 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...
Страница 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
Страница 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...