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74

Pin Descriptions

Chapter 10

AMD Athlon™ XP Processor Model 6 Data Sheet

24309E—March 2002

Preliminary Information

For more information, see the “Required Circuits” chapter of
the 

AMD Athlon™ Processor-Based Motherboard Design Guide

,

order# 24363.

VREFSYS Pin

VREFSYS (W5) drives the threshold voltage for the system bus
input receivers. The value of VREFSYS is system specific. In
addition, to minimiz e VCC_CORE noise rejection from
V R E F S Y S ,   i n c l u d e   d e c o u p l i n g   c a p a c i t o r s .   Fo r   m o re
information, see the 

AMD Athlon™ Processor-Based Motherboard

Design Guide

, order# 24363.

ZN and ZP Pins

ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to VCC_CORE with a resistor
that has a resistance matching the impedance Z

0

 of the

transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z

0

 of the transmission line.

Table 22. VID[4:0] Code to Voltage Definition

VID[4:0]

VCC_CORE (V)

VID[4:0]

VCC_CORE (V)

00000

1.850

10000

1.450

00001

1.825

10001

1.425

00010

1.800

10010

1.400

00011

1.775

10011

1.375

00100

1.750

10100

1.350

00101

1.725

10101

1.325

00111

1.675

10111

1.275

01000

1.650

11000

1.250

01001

1.625

11001

1.225

01010

1.600

11010

1.200

01011

1.575

11011

1.175

01100

1.550

11100

1.150

01101

1.525

11101

1.125

01110

1.500

11110

1.100

01111

1.475

11111

No CPU

Содержание AX1800DMT3C - Athlon XP 1.53 GHz Processor

Страница 1: ...Preliminary Information AMD Athlon XP Processor Model 6 Data Sheet Publication 24309 Rev E Issue Date March 2002 TM...

Страница 2: ...fications and product descriptions at any time without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Exc...

Страница 3: ...t Protocol 13 Connect Protocol 13 Connect State Diagram 17 4 3 Clock Control 19 5 CPUID Support 21 6 Thermal Design 23 7 Electrical Data 25 7 1 Conventions 25 7 2 Interface Signal Groupings 25 7 3 Vol...

Страница 4: ...m and Pin Name Abbreviations 51 10 2 Pin List 60 10 3 Detailed Pin Descriptions 68 A20M Pin 68 AMD Pin 68 AMD Athlon System Bus Pins 68 Analog Pin 68 APIC Pins PICCLK PICD 1 0 68 CLKFWDRST Pin 68 CLKI...

Страница 5: ...Preliminary Information VCCA Pin 73 VID 4 0 Pins 73 VREFSYS Pin 74 ZN and ZP Pins 74 11 Ordering Information 75 Standard AMD Athlon XP Processor Model 6 Products 75 Appendix A Conventions and Abbrevi...

Страница 6: ...vi Table of Contents AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 7: ...nnect Sequence 16 Figure 6 Northbridge Connect State Diagram 17 Figure 7 Processor Connect State Diagram 18 Figure 8 VCC_CORE Voltage Waveform 29 Figure 9 SYSCLK and SYSCLK Differential Clock Signals...

Страница 8: ...viii List of Figures AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 9: ...and SYSCLK AC Characteristics 33 Table 11 AMD Athlon System Bus DC Characteristics 34 Table 12 AMD Athlon System Bus AC Characteristics 35 Table 13 General AC and DC Characteristics 36 Table 14 Therma...

Страница 10: ...x List of Tables AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 11: ...C_CORE Voltage and Current on page 31 In Chapter 11 revised Figure 16 OPN Example for the AMD Athlon XP Processor Model 6 on page 75 November 2001 C Revisions to the AMD Athlon XP Processor Model 6 Da...

Страница 12: ...xii Revision History AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 13: ...peech recognition The AMD Athlon XP processor model 6 also offers the scalability and reliability that IT managers and business users require for enterprise computing The AMD Athlon XP processor model...

Страница 14: ...summarize the AMD Athlon XP processor model 6 QuantiSpeed architecture An advanced nine issue superpipelined superscalar x86 processor microarchitecture designed for increased Instructions Per Cycle...

Страница 15: ...on Figure 1 Typical AMD Athlon XP Processor Model 6 System Block Diagram SDRAM or DDR AGP Bus Memory Bus AGP PCI Bus LAN SCSI LPC Bus USB Dual EIDE AMD Athlon XP Processor Model 6 System Controller No...

Страница 16: ...4 Overview Chapter 1 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 17: ...naling technology contained within the Socket A socket For more information see AMD Athlon System Bus Signals on page 6 Chapter 10 Pin Descriptions on page 51 and the AMD Athlon and AMD Duron System B...

Страница 18: ...nce of the motherboard by two external resistors connected to the ZN and ZP pins See ZN and ZP Pins on page 74 for more information 2 4 AMD Athlon System Bus Signals The AMD Athlon system bus is a clo...

Страница 19: ...e 2 Logic Symbol Diagram SDATA 63 0 SDATAINCLK 3 0 SDATAOUTCLK 3 0 Data SADDIN 14 2 SADDINCLK Probe SysCMD SADDOUT 14 2 SADDOUTCLK VID 4 0 FID 3 0 A20M CLKFWDRST CONNECT COREFB COREFB FERR IGNNE INIT...

Страница 20: ...8 Logic Symbol Diagram Chapter 3 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 21: ...agement states of the processor The figure includes the ACPI Cx naming convention for these states Figure 3 AMD Athlon XP Processor Model 6 Power Management States C1 Halt C0 Working4 Execute HLT SMI...

Страница 22: ...t if it is disconnected then issue a Stop Grant special cycle When STPCLK is deasserted the processor will exit the Stop Grant state and re enter the Halt state The processor will issue a Halt special...

Страница 23: ...nt state the processor exits the Stop Grant state and the reset process begins There are two mechanisms for asserting STPCLK hardware and software The Southbridge can force STPCLK assertion for thrott...

Страница 24: ...of the S1 Stop Grant state when any enabled resume event occurs Probe State The Probe state is entered when the Northbridge connects the AMD Athlon system bus to probe the processor for example to sn...

Страница 25: ...ant Reconnect is initiated by the processor in response to an interrupt for Halt or STPCLK deassertion Reconnect is initiated by the Northbridge to probe the processor The Northbridge contains BIOS pr...

Страница 26: ...e to the Northbridge but before the disconnect actually occurs In this case the processor sends the Connect special cycle to the Northbridge rather than continuing with the disconnect sequence In resp...

Страница 27: ...rant state 2 When the processor recognizes STPCLK asserted it enters the Stop Grant state and then issues a Stop Grant special cycle 3 When the special cycle is received by the Northbridge it deassert...

Страница 28: ...moves the processor from the Stop Grant state and connects it to the system bus 1 The Southbridge deasserts STPCLK informing the processor of a wake event 2 When the processor recognizes STPCLK deasse...

Страница 29: ...special cycle from the processor 4 No probes are pending 5 PROCRDY is deasserted 6 A probe needs service 7 PROCRDY is asserted 8 Three SYSCLK periods after CLKFWDRST is deasserted Although reconnecte...

Страница 30: ...RST is deasserted by the Northbridge 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted Action A CLKFWDRST is asserted by the Northbridge B Issue a Connect special cycle C Retur...

Страница 31: ...Clock Control The processor implements a Clock Control CLK_Ctl MSR address C001_001Bh that determines the internal clock divisor when the AMD Athlon system bus is disconnected Refer to the AMD Athlon...

Страница 32: ...20 Power Management Chapter 4 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 33: ...about the processor vendor type name etc and its capabilities Software can make use of this information to accurately tune the system for maximum performance and benefit to users For information on th...

Страница 34: ...22 CPUID Support Chapter 5 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 35: ...is Cooling Design Guide order 23794 and the cooling guidelines on http www amd com Table 1 shows the thermal design power specifications for the AMD Athlon XP processor model 6 Table 1 Thermal Design...

Страница 36: ...24 Thermal Design Chapter 6 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 37: ...REFB See Absolute Ratings on page 30 Voltage Identification VID 4 0 on page 26 VID 4 0 Pins on page 73 on page 27 VCCA Pin on page 73 and COREFB and COREFB Pins on page 69 Frequency FID 3 0 See Freque...

Страница 38: ...BYPASS PLLTEST PLLMON1 PLLMON2 SCANCLK1 SCANCLK2 SCANSHIFTEN SCANINTEVAL ANALOG See General AC and DC Characteristics on page 36 PLL Bypass and Test Pins on page 72 Scan Pins on page 72 Analog Pin on...

Страница 39: ...3 or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD Athlon XP processor model 6 Table 4 FID 3 0 DC Characteristics Parameter Descri...

Страница 40: ...29 Table 6 VCC_CORE AC and DC Characteristics Symbol Parameter Limit in Working State Units VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM 50 mV VCC_CORE_DC_MIN Maximum static voltage below...

Страница 41: ...waveform response to perturbation The tMIN_AC negative AC transient excursion time and tMAX_AC positive AC transient excursion time represent the maximum allowable time below or above the DC tolerance...

Страница 42: ...ly affect long term reliability or result in functional damage Table 7 lists the maximum absolute ratings of operation for the AMD Athlon XP processor model 6 Table 7 Absolute Ratings Parameter Descri...

Страница 43: ...ing the Sleep state but customers should test their systems in Sleep state to ensure that the system when using typical parts has adequate cooling without the fan during the Sleep state to meet the te...

Страница 44: ...ial Clock Signals Table 9 SYSCLK and SYSCLK DC Characteristics Symbol Description Min Max Units VThreshold DC Crossing before transition is detected DC 400 mV VThreshold AC Crossing before transition...

Страница 45: ...Time 2 ns t5 Rise Time 2 ns Period Stability 300 ps Notes 1 Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed loop jitter bandwidth to allow the PLL to track...

Страница 46: ...istate Leakage Pulldown VIN VREF Nominal 100 A VIH Input High Voltage VREF 200 VCC_CORE 500 mV VIL Input Low Voltage 500 VREF 200 mV VOH Output High Voltage IOUT 200 A 0 85 VCC_CORE VCC_CORE 500 mV 2...

Страница 47: ...4 12 pF Sync TVAL RSTCLK to Output Valid 250 2000 ps 4 5 TSU Setup to RSTCLK 500 ps 4 6 THD Hold from RSTCLK 1000 ps 4 6 Notes 1 Rise and fall time ranges are guidelines over which the I O has been ch...

Страница 48: ...ply voltage range 2 Values specified at nominal VCC_CORE Scale parameters between VCC_CORE minimum and VCC_CORE maximum 3 IOL and IOH are measured at VOL max and VOH min respectively 4 Synchronous inp...

Страница 49: ...e specified with respect to RSTCLK and RSTCK at the pins 5 These are aggregate numbers 6 Edge rates indicate the range over which inputs were characterized 7 In asynchronous operation the signal must...

Страница 50: ...tomated Test Equipment ATE to test for validity on open drain pins Refer to Table 13 General AC and DC Characteristics on page 36 for timing requirements Figure 11 General ATE Open Drain Test Circuit...

Страница 51: ...e ideal diode equation For the following equations use the following variables and constants n Diode ideality factor k Boltzmann constant q Electron charge constant T Diode temperature Kelvin VBE Volt...

Страница 52: ...cessor Systems that do not implement thermal protection circuitry or that do not react within the time specified by TSD_DELAY can cause thermal damage to the processor during the unlikely events of fa...

Страница 53: ...ode for measuring die temperature of the processor The processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdow...

Страница 54: ...42 Electrical Data Chapter 7 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 55: ...ing Description Figure 12 shows the relationship between key signals in the system during a power up sequence This figure details the requirements of the processor Figure 12 Signal Relationship Requir...

Страница 56: ...conds from the 3 3 V supply being within specification This delay ensures that the system clock SYSCLK SYSCLK is operating within specification when PWROK is asserted The processor core voltage VCC_CO...

Страница 57: ...eet the timing requirements as defined in Table 13 General AC and DC Characteristics on page 36 The processor should not switch between the ring oscillator and the PLL after the initial assertion of P...

Страница 58: ...0 code The SIP is sent to the processor using the SIP protocol This protocol uses the PROCRDY CONNECT and CLKFWDRST signals that are synchronous to SYSCLK For more information about FID 3 0 see FID 3...

Страница 59: ...ates heat transfer from the die to an approved heat sink It is critical that the mechanical loading of the heat sink does not exceed the limits shown in Table 17 Any heat sink design should avoid load...

Страница 60: ...Dimensions for the AMD Athlon XP Processor Model 6 OPGA Package Letter or Symbol Minimum Dimension Maximum Dimension Letter or Symbol Minimum Dimension Maximum Dimension D E 49 27 49 78 G H 4 50 D1 E1...

Страница 61: ...Chapter 9 Mechanical Data 49 24309E March 2002 AMD Athlon XP Processor Model 6 Data Sheet Preliminary Information Figure 13 AMD Athlon XP Processor Model 6 OPGA Package...

Страница 62: ...50 Mechanical Data Chapter 9 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 63: ...eviations Figure 14 on page 52 shows the staggered Pin Grid Array PGA for the AMD Athlon XP processor model 6 Because some of the pin names are too long to fit in the grid they are abbreviated Figure...

Страница 64: ...VCC VSS VSS VSS VSS R S SCNCK1 SCNINV SCNCK2 THDA NC SD 7 SD 15 SD 6 S T VSS VSS VSS VSS VCC VCC VCC VCC T U TDI TRST TDO THDC NC SD 5 SD 4 NC U V VCC VCC VCC VCC VSS VSS VSS VSS V W FID 0 FID 1 VREF...

Страница 65: ...Y KEY NC CLKIN CLKIN 17 18 VSS VSS VSS VSS VCC VCC VCC VCC 18 19 NC SD 59 SD 58 NC NC NC RCLK RCLK 19 20 VCC VCC VCC VCC VSS VSS VSS VSS 20 21 SD 57 SD 56 SD 36 NC NC CLKFR K7CO K7CO 21 22 VSS VSS VSS...

Страница 66: ...W3 FID 2 Y1 FID 3 Y3 FLUSH AL3 IGNNE AJ1 INIT AJ3 INTR AL1 K7CO K7CLKOUT AL21 K7CO K7CLKOUT AN21 KEY G7 KEY G9 KEY G15 KEY G17 KEY G23 KEY G25 KEY N7 KEY Q7 KEY Y7 KEY AA7 KEY AG7 KEY AG9 KEY AG15 KE...

Страница 67: ...LBYC PLLBYPASSCLK AN15 PLBYC PLLBYPASSCLK AL15 PLMN1 PLLMON1 AN13 PLMN2 PLLMON2 AL13 PLTST PLLTEST AC3 PRCRDY PROCREADY AN23 PWROK AE3 RESET AG3 RCLK RSTCLK AN19 RCLK RSTCLK AL19 SAI 0 SADDIN 0 AJ29 S...

Страница 68: ...23 G35 SD 24 SDATA 24 Q33 SD 25 SDATA 25 N33 SD 26 SDATA 26 L33 SD 27 SDATA 27 N35 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin SD 28 SDATA 28 L37 SD 29 SDATA 29 J37 SD 30 SDA...

Страница 69: ...CORE D28 VCC VCC_CORE D32 VCC VCC_CORE F12 VCC VCC_CORE F16 VCC VCC_CORE F20 VCC VCC_CORE F24 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin VCC VCC_CORE F28 VCC VCC_CORE F32 VCC...

Страница 70: ...RE AK18 VCC VCC_CORE AK22 VCC VCC_CORE AK26 VCC VCC_CORE AK30 VCC VCC_CORE AK34 VCC VCC_CORE AK36 VCC VCC_CORE AJ5 VCC VCC_CORE AL5 VCC VCC_CORE AM2 VCC VCC_CORE AM10 VCC VCC_CORE AM14 VCC VCC_CORE AM...

Страница 71: ...VSS X4 VSS X6 VSS X8 VSS Z30 VSS Z32 VSS Z34 VSS Z36 VSS AB2 VSS AB8 VSS AB4 VSS AB6 VSS AD32 Table 19 Pin Name Abbreviations continued Abbreviation Full Name Pin VSS AD34 VSS AD36 VSS AF2 VSS AF4 VS...

Страница 72: ...VSS B20 VCC_CORE B22 VSS B24 VCC_CORE B26 VSS B28 VCC_CORE B30 VSS B32 VCC_CORE B34 VSS B36 VCC_CORE C1 SADDOUT 7 P O G Table 20 Cross Reference by Pin Location Pin Name Description L P R 10 2 Pin Li...

Страница 73: ...RE D18 VSS D20 VCC_CORE D22 VSS D24 VCC_CORE D26 VSS D28 VCC_CORE D30 VSS D32 VCC_CORE Table 20 Cross Reference by Pin Location Pin Name Description L P R D34 VSS D36 VSS E1 SADDOUT 11 P O P E3 SADDOU...

Страница 74: ...72 H8 NC Pin page 72 H10 NC Pin page 72 H12 VCC_CORE H14 VSS H16 VCC_CORE H18 VSS H20 VCC_CORE Table 20 Cross Reference by Pin Location Pin Name Description L P R H22 VSS H24 VCC_CORE H26 VSS H28 NC...

Страница 75: ...B P Q35 SDATA 17 P B G Q37 SDATA 16 P B G R2 VCC_CORE R4 VCC_CORE R6 VCC_CORE R8 VCC_CORE Table 20 Cross Reference by Pin Location Pin Name Description L P R R30 VSS R32 VSS R34 VSS R36 VSS S1 SCANCLK...

Страница 76: ...E Z4 VCC_CORE Z6 VCC_CORE Z8 VCC_CORE Z30 VSS Z32 VSS Z34 VSS Z36 VSS Table 20 Cross Reference by Pin Location Pin Name Description L P R AA1 DBRDY page 69 P O AA3 DBREQ page 69 P I AA5 NC AA7 Key Pin...

Страница 77: ...page 69 AG13 COREFB page 69 AG15 Key Pin page 71 AG17 Key Pin page 71 AG19 NC Pin page 72 Table 20 Cross Reference by Pin Location Pin Name Description L P R AG21 NC Pin page 72 AG23 NC Pin page 72 A...

Страница 78: ...RE AL1 INTR page 71 P I AL3 FLUSH page 71 P I AL5 VCC_CORE AL7 NC Pin page 72 Table 20 Cross Reference by Pin Location Pin Name Description L P R AL9 NC Pin page 72 AL11 NC Pin page 72 AL13 PLLMON2 pa...

Страница 79: ...in page 72 AN13 PLLMON1 page 72 O B AN15 PLLBYPASSCLK page 72 P I AN17 CLKIN page 68 P I P AN19 RSTCLK page 68 P I P AN21 K7CLKOUT page 71 P O AN23 PROCRDY P O P AN25 NC Pin page 72 AN27 NC Pin page 7...

Страница 80: ...on System Bus Specification order 21902 for information about the system bus pins PROCRDY PWROK RESET SADDIN 14 2 SADDINCLK SADDOUT 14 2 SADDOUTCLK SDATA 63 0 SDATAINCLK 3 0 SDATAINVALID SDATAOUTCLK 3...

Страница 81: ...SS on the processor package If pulled up on the motherboard CPU_PRESENCE may be used to detect the presence or absence of a processor in the Socket A style socket DBRDY and DBREQ Pins DBRDY and DBREQ...

Страница 82: ...Bus Specification order 21902 for more information about Serialization Initialization Packets and SIP protocol Table 21 FID 3 0 Clock Multiplier Encodings FID 3 0 2 Processor Clock to SYSCLK Frequency...

Страница 83: ...arts at 0_FFFF_FFF0h INTR Pin INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8 bit interrupt vector and starts execution at t...

Страница 84: ...d to the debug connector All four processor inputs PLLTEST PLLBYPASS PLLMON1 and PLLMON2 are tied to VCC_CORE with pullup resistors PWROK Pin The PWROK input to the processor must not be asserted unti...

Страница 85: ...de pins are used to monitor the actual temperature of the processor die providing more accurate temperature control to the system See Table 14 Thermal Diode Electrical Characteristics on page 39 for m...

Страница 86: ...P AE5 are the push pull compensation circuit pins In Push Pull mode selected by the SIP parameter SysPushPull asserted ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedan...

Страница 87: ...Figure 16 Figure 16 OPN Example for the AMD Athlon XP Processor Model 6 A 2100 D M T 3 C Note Spaces are added to the number shown above for viewing clarity only OPN Max FSB C 266 MHz Size of L2 Cach...

Страница 88: ...76 Ordering Information Chapter 11 AMD Athlon XP Processor Model 6 Data Sheet 24309E March 2002 Preliminary Information...

Страница 89: ...Ranges In a range of signals the highest and lowest signal numbers are contained in brackets and separated by a colon for example D 63 0 Reserved Bits and Signals Signals or bus bits marked reserved...

Страница 90: ...te with the address xx xx00 is in the least significant byte position little end In byte diagrams bit positions are numbered from right to left the little end is on the right and the big end is on the...

Страница 91: ...ument Table 23 Abbreviations Abbreviation Meaning A Ampere F Farad G Giga Gbit Gigabit Gbyte Gigabyte H Henry h Hexadecimal K Kilo Kbyte Kilobyte M Mega Mbit Megabit Mbyte Megabyte MHz Megahertz m Mil...

Страница 92: ...rrupt Controller BIOS Basic Input Output System BIST Built In Self Test BIU Bus Interface Unit CPGA Ceramic Pin Grid Array DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access...

Страница 93: ...ect PDE Page Directory Entry PDT Page Directory Table PGA Pin Grid Array PLL Phase Locked Loop PMSM Power Management State Machine POS Power On Suspend POST Power On Self Test RAM Random Access Memory...

Страница 94: ...heet 24309E March 2002 Preliminary Information TTL Transistor Transistor Logic VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus ZDB Zero Delay Buf...

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