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AC101
Preliminary Data Sheet
06/04/01
B r o a d c o m
Page 2
MAC Interface
Document AC101-DS01-405-R¥¥¥¥¥
Independent Interface) 100 PCS Bypass Pins” on page 12). MDC is a clock input to the PHY which is used to latch in or out
data and instructions for the PHY. The clock can run at any speed from DC to 25 MHz. MDIO is a bi-directional connection
used to write instructions to, write data to, or read data from the PHY. Each data bit is latched either in or out on the rising
edge of MDC. MDC is not required to maintain any speed or duty cycle, provided no half cycle is less than 20ns and that
data is presented synchronous to MDC.
MDC/MDIO are a common signal pair to all PHYs on a design. Therefore, each PHY needs to have its own unique Physical
Address. The Physical Address of the PHY is set using the pins defined as PHYAD[4:0] (see ”PHY Address Pins” on page
11). These input signals are strapped externally and sampled as reset is negated. At idle, the PHY is responsible to pull
MDIO line to a high state. Therefore, a 1.5K Ohms resistor is required to connect MDIO line to Vcc. The PHYAD can be
reprogrammed via software. A detailed definition of the Serial Management registers follows.
At the beginning of a read or write cycle, the MAC will send a continuous 32 bits of one at the MDC clock rate to indicate
preamble. A zero and a one will follow to indicate start of frame. A read OP code is a one and a zero, while a write OP code
is a zero and a one. These will be followed by 5 bits to indicate PHY address and 5 bits to indicate register address. Then 2
bits follow to allow for turn around time. For read operation, the first bit will be high impedance. Neither the PHY nor the
station will assert this bit. During the second bit time, the PHY will assert this bit to a zero. For write operation, the station
will drive a one for the first bit time, and a zero for the second bit time. The 16 bits data field is then presented. The first bit
that is transmitted is bit 15 of the register content.
Interrupts
The INTR pin (see ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12) on the PHY will be asserted when-
ever one of 8 selectable interrupt events occur. Assertion state is programmable to either high or low through the INTR_LEVL
register bit (see ”Register 16: Polarity and Interrupt Level Register” on page 29). Selection is made by setting the appropriate
bit in the upper half of the Interrupt Control/Status register (see ”Register 17: Interrupt Control/Status Register” on page 30).
When the INTR bit goes active, the MAC interface is required to read the Interrupt Control/Status register to determine which
event caused the interrupt. The Status bits are read only and clear on read. When INTR is not asserted, the pin is held in a
high impedance state.
Carrier Sense/RX_DV
Carrier sense is asserted asynchronously on the CRS pins as soon as activity is detected on the receive data stream.
RX_DV is asserted as soon as a valid SSD (Start-of-Stream Delimiter) is detected. Carrier sense and RX_DV are de-assert-
ed synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data
stream. However, if the carrier sense is asserted and a valid SSD is not detected immediately, RX_ER is asserted instead
of RX_DV. See ”MII (Media Independent Interface) 100 PCS Bypass Pins” on page 12.)
In 10BASE-T mode, CRS is asserted asynchronously when the valid preamble and data activity is detected on the RXIP and
RXIN pins.
In the half-duplex mode, the CRS is activated during the transmit and receiving of data. In the full-duplex mode, the CRS is
activated during data reception only.
7-W
IRE
S
ERIAL
I
NTERFACE
To allow the PHY to run in legacy 10 Mbps only designs, the 7-wire serial interface, referred to as General Purpose Serial
Interface (GPSI, see ”10 Mbps 7-Wire Interface Pins” on page 13) has been included. GPSI is an industry standard interface
which has been implemented in many micro-controllers and micro-processors, as well as the majority of the 10 Mpbs MACs.
The interface consists of 10 Mbps transmit and receive clocks, 10 Mbps serial transmit and receive data, transmit enable,
receive enable and collision.
When running the GPSI mode, the PHY must be forced to 10 Mbps only mode through hardware configuration.
The 10BASE-T 7-wire interface is enabled when the GPIO[0] (see ”Control and Status Pins” on page 14) is pull low by 1 K
Ω
during reset.
