Enpirion
®
Power Evaluation Board User Guide
EP5358xUI PowerSoC
V
IN
V
Sense
V
S0
V
S2
E
P
5
3
5
8
L
U
I
10
µ
F
0805
4.7
µ
F
0603
V
OUT
V
OUT
AGND
ENABLE
R1
R2
V
FB
V
S1
PGND
AVIN
PVIN
Figure 3. External divider schematic for the EP5358LUI.
The output voltage is selected by the following formula:
(
)
2
1
1
6
.
0
R
R
OUT
V
V
+
=
R
1
must be chosen as 237k
Ω
to maintain control loop stability. Then R
2
is given
as:
Ω
−
=
6
.
0
10
2
.
142
3
2
OUT
V
x
R
The external voltage divider option is chosen by setting the jumpers VS0 – VS2
to a logic “high”.
Note:
The V
SENSE
pin should be tied to the Output pin even in external feedback
mode to access the internal phase lead capacitor that is situated between the
V
SENSE
and V
FB
pads. This phase lead capacitor is integral to the loop
compensation and the power supply stability.
Dynamically Adjustable Output
The EP5358xUI is designed to allow for dynamic switching between the
predefined voltage levels by toggling the VID pins. The inter-voltage slew rate is
optimized to prevent excess undershoot or overshoot as the output voltage levels
transition. The slew rate is defined in the datasheet.
This feature can be tested by connecting the VSx jumper center pins to logic
driver to toggle between the various V
OUT
states.
Page 6 of 10
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