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DE5-Net User Manual
June 20, 2018
25
FSM_D26
Data bus
2.5-V
PIN_AV31
FSM_D27
Data bus
2.5-V
PIN_AV32
FSM_D28
Data bus
2.5-V
PIN_BC31
FSM_D29
Data bus
2.5-V
PIN_AW30
FSM_D30
Data bus
2.5-V
PIN_BC32
FSM_D31
Data bus
2.5-V
PIN_BD31
FLASH_CLK
Clock
2.5-V
PIN_AL29
FLASH_RESET_n
Reset
2.5-V
PIN_AE28
FLASH_CE_n[0]
Chip enable of of flash-0
2.5-V
PIN_AE27
FLASH_CE_n[1]
Chip enable of of flash-1
2.5-V
PIN_BA31
FLASH_OE_n
Output enable
2.5-V
PIN_AY30
FLASH_WE_n
Write enable
2.5-V
PIN_AR31
FLASH_ADV_n
Address valid
2.5-V
PIN_AK29
FLASH_RDY_BSY_n[0] Ready of flash-0
2.5-V
PIN_BA29
FLASH_RDY_BSY_n[1] Ready of flash-1
2.5-V
PIN_BB32
2
2
.
.
8
8
D
D
D
D
R
R
3
3
S
S
O
O
-
-
D
D
I
I
M
M
M
M
The development board supports two independent banks of DDR3 SDRAM SO-DIMM. Each
DDR3 SODIMM socket is wired to support a maximum capacity of 8GB with a 64-bit data bus.
Using differential DQS signaling for the DDR3 SDRAM interfaces, it is capable of running at up to
800MHz memory clock for a maximum theoretical bandwidth up to 95.4Gbps.
Figure 2-13
shows
the connections between the DDR3 SDRAM SO-DIMMs and Stratix V GX FPGA.