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Chapter 2: Board Components
2–31
Components and Transceiver Interfaces
August 2015
Altera Corporation
Cyclone IV GX FPGA Development Board
Reference Manual
Table 2–33
lists the HSMC port A interface pin assignments, signal names, and
functions.
Table 2–33. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Cyclone IV GX
Device
Pin Number
J1.17
Transceiver TX bit 3
HSMA_TX_P3
1.5 V
H4
J1.19
Transceiver TX bit 3n
HSMA_TX_N3
H3
J1.18
Transceiver RX bit 3
HSMA_RX_P3
J2
J1.20
Transceiver RX bit 3n
HSMA_RX_N3
J1
J1.21
Transceiver TX bit 2
HSMA_TX_P2
K4
J1.23
Transceiver TX bit 2n
HSMA_TX_N2
K3
J1.22
Transceiver RX bit 2
HSMA_RX_P2
L2
J1.24
Transceiver RX bit 2n
HSMA_RX_N2
L1
J1.25
Transceiver TX bit 1
HSMA_TX_P1
M4
J1.27
Transceiver TX bit 1n
HSMA_TX_N1
M3
J1.26
Transceiver RX bit 1
HSMA_RX_P1
N2
J1.28
Transceiver RX bit 1n
HSMA_RX_N1
N1
J1.29
Transceiver TX bit 0
HSMA_TX_P0
P4
J1.31
Transceiver TX bit 0n
HSMA_TX_N0
P3
J1.30
Transceiver RX bit 0
HSMA_RX_P0
R2
J1.32
Transceiver RX bit 0n
HSMA_RX_N0
2.5-V
R1
J1.33
Management serial data
HSMA_T_SDA
C25
J1.34
Management serial clock
HSMA_T_SCL
B24
J1.35
JTAG clock signal
JTAG_TCK
F2
J1.36
JTAG mode select signal
JTAG_TMS
E1
J1.37
JTAG data output
HSMA_JTAG_TDO
—
J1.38
JTAG data input
HSMA_JTAG_TDI
2.5-V
—
J1.39
Dedicated CMOS clock out
HSMA_CLK_OUT0
—
J1.40
Dedicated CMOS clock in
HSMA_CLK_IN0
—
J1.41
Dedicated CMOS I/O bit 0
HSMA_D0
AC27
J1.42
Dedicated CMOS I/O bit 1
HSMA_D1
Y27
J1.43
Dedicated CMOS I/O bit 2
HSMA_D2
AF30
J1.44
Dedicated CMOS I/O bit 3
HSMA_D3
AD27