November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
4. Parameter Settings
This chapter describes the parameters which you can set using the MegaWizard
Plug-In Manager or Qsys design flow to instantiate a Arria V GZ Hard IP for PCI
Express. This chapter also describes the parameters which you can set for the
Avalon-MM Arria V GZ Hard IP for PCI Express in the Qsys design flow. For the most
part, the two Arria V GZ Hard IPs for PCI Express offer almost the same parameters
as
indicates.
1
In the following tables, hexadecimal addresses in
green
are links to additional
Chapter 7, Register Descriptions
System Settings
The first group of settings defines the overall system.
describes these
settings.
Table 4–1. Parameters Available for the Arria V GZ Hard IP for PCI Express
Parameter Group
Application Layer Interface
Avalon-ST
Avalon-MM
v
v
Base Address Register (BAR) and Expansion ROM Settings
v
v
Base and Limit Registers for Root Ports
v
Device Identification Registers
v
v
PCI Express and PCI Capabilities Parameters
v
v
v
v
v
v
v
v
v
v
v
v
Avalon Memory-Mapped System Settings
—
v
Avalon to PCIe Address Translation Settings
—
v
:
(1) The Avalon-MM Arria V GZ Hard IP for PCI Express do not filter incoming addresses.
Table 4–2. System Settings for PCI Express (Part 1 of 4)
Parameter
Value
Description
Number of Lanes
×1, ×2, ×4, ×8
Specifies the maximum number of lanes supported.
Lane Rate
Gen1 (2.5 Gbps)
Gen2 (2.5/5.0 Gbps)
Gen3 (2.5/5.0/8.0 Gbps)
Specifies the maximum data rate at which the link can operate. Gen3 is
only supported for Arria V GZ production devices.
November 2012
UG-01097-1.4